Projects per year
Personal profile
Research Interests
· Computer Architecture
· Computer Systems
· Memory and Storage Systems
· Domain-specific Accelerators (GPU, Neural Processing Units)
Education/Academic qualification
PhD, Electrical Engineering, Purdue University
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Dive into the research topics where Tsung-Tai Yeh is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫二；高效能，低功耗邊緣AI計算加速器架構系統設計
Yeh, T.-T. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫-111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-智慧終端裝置晶片系統與應用模組-邊緣 AI 加速器架構於微型深度學習網路模型
Yeh, T.-T. (PI)
1/04/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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Optimizing Domain-Specific Accelerator Hardware Resource Utilization
Yeh, T.-T. (PI)
1/11/21 → 1/01/23
Project: Government Ministry › Other Government Ministry Institute
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OC-DLRM: Minimizing the I/O Traffic of DLRM Between Main Memory and OCSSD
Ti, S. H., Chen, T. Y., Yeh, T. T., Chen, S. H. & Liang, Y. P., 2024, 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings -Design, Automation and Test in Europe, DATE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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TinyTS: Memory-Efficient TinyML Model Compiler Framework on Microcontrollers
Liu, Y. Y., Zheng, H. S., Fang Hu, Y., Hsu, C. F. & Yeh, T. T., 2024, Proceedings - 2024 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2024. IEEE Computer Society, p. 848-860 13 p. (Proceedings - International Symposium on High-Performance Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR
Huang, E. M., Cheng, B. W., Lin, M. H., Lee, C. Y. & Yeh, T. T., 2024, ASP-DAC 2024 - 29th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 201-206 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPU
Cheng, B. W., Huang, E. M., Chao, C. H., Sun, W. F., Yeh, T. T. & Lee, C. Y., 16 Jan 2023, ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 314-319 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
StreamNet: Memory-Efficient Streaming Tiny Deep Learning Inference on the Microcontroller
Zheng, H. S., Hsu, C. F., Liu, Y. Y. & Yeh, T. T., 2023, In: Advances in Neural Information Processing Systems. 36Research output: Contribution to journal › Conference article › peer-review
1 Scopus citations