Personal profile
Research Interests
Digital IP Authoring, VLSI/IC Design, Signal Processing Architecture Design, Image and Video Signal Processing, Computer Architecture Design
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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Collaborations and top research areas from the last five years
Projects
- 25 Finished
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高效脈衝神經網絡硬體加速器研究
Chang, T.-S. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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高效脈衝神經網絡硬體加速器研究
Chang, T.-S. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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智慧晶片系統與應用人才培育計畫-智慧終端裝置晶片系統與應用聯盟111年度計畫
Chang, T.-S. (PI)
1/08/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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高效脈衝神經網絡硬體加速器研究
Chang, T.-S. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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智慧晶片系統與應用人才培育計畫-智慧終端裝置晶片系統與應用聯盟110年度計畫
Chang, T.-S. (PI)
1/07/21 → 31/07/22
Project: Government Ministry › Ministry of Education(Include School)
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Low-Power Vision Transformer Accelerator With Hardware-Aware Pruning and Optimized Dataflow
Hsiung, C. L. & Chang, T. S., 2026, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 73, 1, p. 360-369 10 p.Research output: Contribution to journal › Article › peer-review
Open Access2 Scopus citations -
A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse
Hsu, K. C. & Chang, T. S., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An Efficient Data Reuse with Tile-Based Adaptive Stationary for Transformer Accelerators
Li, T. J. & Chang, T. S., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
Hardware Efficient Accelerator for Spiking Transformer With Reconfigurable Parallel Time Step Computing
Chen, B. Y. & Chang, T. S., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
A 71.2-μW Speech Recognition Accelerator with Recurrent Spiking Neural Network
Yang, C. C. & Chang, T. S., 1 Jul 2024, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 71, 7, p. 3203-3213 11 p.Research output: Contribution to journal › Article › peer-review
4 Scopus citations