Projects per year
Personal profile
Research Interests
Digital IP Authoring, VLSI/IC Design, Signal Processing Architecture Design, Image and Video Signal Processing, Computer Architecture Design
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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- 1 Similar Profiles
Collaborations and top research areas from the last five years
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智慧晶片系統與應用人才培育計畫-智慧終端裝置晶片系統與應用聯盟111年度計畫
1/08/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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智慧晶片系統與應用人才培育計畫-智慧終端裝置晶片系統與應用聯盟110年度計畫
1/07/21 → 31/07/22
Project: Government Ministry › Ministry of Education(Include School)
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A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation
Yang, C. C. & Chang, T. S., 2023, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-10 10 p.Research output: Contribution to journal › Article › peer-review
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Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing
Huang, A. J., Hung, J. H. & Chang, T. S., 1 Jun 2023, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31, 6, p. 802-811 10 p.Research output: Contribution to journal › Article › peer-review
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A 14 μJ/Decision Keyword Spotting Accelerator With In-SRAM-Computing and On Chip Learning for Customization
Chiang, Y. H., Chang, T-S. & Jou, S. J., 2022, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-9 9 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
All Attention U-NET for Semantic Segmentation of Intracranial Hemorrhages In Head CT Images
Shuo Chang, C., Sheuan Chang, T., Lin Yan, J. & Ko, L., 2022, BioCAS 2022 - IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 600-604 5 p. (BioCAS 2022 - IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications
Liu, C., Li, S. T., Pan, T. L., Ni, C. E., Sung, Y., Hu, C. L., Chang, K. Y., Hou, T. H., Chang, T. S. & Jou, S. J., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations