世傑 周

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Shyh-Jye Jerry Jou

Professor

Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
1900 …2024

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  • 2012

    An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

    Lin, G. C., Wang, S. C., Lin, Y. W., Tsai, M. C., Chuang, C. T., Jou, S.-J., Lien, N. C., Shih, W. C., Lee, K. D. & Chu, J. K., 28 Sep 2012, p. 2485-2488. 4 p.

    Research output: Contribution to conference › Paper › peer-review

    2 Scopus citations

  • High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

    Yang, H. I., Lin, Y. W., Hsia, M. C., Lin, G. C., Chang, C. S., Chen, Y. N., Chuang, C. T., Hwang, W., Jou, S.-J., Lien, N. C., Li, H. Y., Lee, K. D., Shih, W. C., Wu, Y. P., Lee, W. T. & Hsu, C. C., 2012, p. 1831-1834. 4 p.

    Research output: Contribution to conference › Paper › peer-review

    1 Scopus citations
  • 2004

    A module generator for parameterized DSP core

    Tsao, Y. L., Lin, Y. C., Chen, W. H., Huang, B. S. & Jou, S.-J., Dec 2004, p. 361-364. 4 p.

    Research output: Contribution to conference › Paper › peer-review

    1 Scopus citations

  • Low power correlator of DSP core for communication system

    Tsao, Y. L., Teng, J. X., Lin, M. C. & Jou, S.-J., Dec 2004, p. 217-220. 4 p.

    Research output: Contribution to conference › Paper › peer-review

  • 2000

    Fixed-width multiplier for DSP application

    Jou, S.-J. & Wang, H. H., 1 Jan 2000, p. 318-322. 5 p.

    Research output: Contribution to conference › Paper › peer-review

    38 Scopus citations
  • 1998

    All digital phase-locked loop with modified binary search of frequency acquisition

    Jou, S.-J., Tsao, Y. L. & Yang, I. Y., 1 Dec 1998, p. 195-198. 4 p.

    Research output: Contribution to conference › Paper › peer-review

    3 Scopus citations
  • 1997

    Low-voltage low-power IF-baseband digital down converter

    Jou, S.-J., Hsu, T. I. & Wang, C. K., 1997, p. 270-274. 5 p.

    Research output: Contribution to conference › Paper › peer-review

  • Structural approach for performance driven ECC circuit synthesis

    Su, C.-C., Chen, K. Y. & Jou, S.-J., 1 Jan 1997, p. 89-94. 6 p.

    Research output: Contribution to conference › Paper › peer-review

    1 Scopus citations
  • 1984

    MOTA - AN MOS TIMING SIMULATOR.

    Jou, S.-J., Jen, C. W., Shen, W. Z. & Lee, C. L., 1984, p. 10-11. 2 p.

    Research output: Contribution to conference › Paper › peer-review