柏蒼 黃

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Po-Tsang Huang

Associate Professor

 https://orcid.org/0000-0001-8679-2755
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
20042024

Research activity per year

Search results

  • 2009

    STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME

    Hwang, W. (Inventor) & Huang, P.-T. (Inventor), 28 Apr 2009, Patent No. 7525827B2

    Research output: Patent

  • SUPER LEAKAGE CURRENT CUT-OFF DEVICE FOR TERNARY CONTENT ADDRESSABLE MEMORY

    Huang, P.-T. (Inventor) & Hwang, W. (Inventor), 10 Nov 2009, Patent No. 7616469B2

    Research output: Patent

  • 2008

    A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop

    Chuang, L. P., Chang, M. H., Huang, P.-T., Kan, C. H. & Hwang, W., 2008, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 3342-3345 4 p. 4542174. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    6 Scopus citations

  • A robust ultra-low power asynchronous FIFO memory with self-adaptive power control

    Chang, M. T., Huang, P.-T. & Hwang, W., 2008, 2008 IEEE International SOC Conference, SOCC. p. 175-178 4 p. 4641505. (2008 IEEE International SOC Conference, SOCC).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    6 Scopus citations

  • Energy-efficient design for ternary content addressable memory

    Huang, P.-T., Chang, S. W., Liu, W. Y. & Hwang, W., 1 Apr 2008, In: International Journal of Electrical Engineering. 15, 2, p. 97-108 12 p.

    Research output: Contribution to journal › Article › peer-review

    1 Scopus citations

  • "Green" micro-architecture and circuit co-design for ternary content addressable memory

    Huang, P.-T., Chang, S. W., Liu, W. Y. & Hwang, W., 19 Sep 2008, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 3322-3325 4 p. 4542169. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    10 Scopus citations

  • Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip

    Huang, P.-T., Fang, W. L., Wang, Y. L. & Hwang, W., 28 May 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 77-83 7 p. 4492727. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    22 Scopus citations
  • 2007

    A 256×128 energy-efficient TCAM with novel low power schemes

    Huang, P.-T., Chang, S. W., Liu, W. Y. & Hwang, W., 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239396. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    16 Scopus citations

  • A 65nm low power 2T1D embedded dram with leakage current reduction

    Chang, M. T., Huang, P.-T. & Hwang, W., 2007, Proceedings - 20th Anniversary IEEE International SOC Conference. p. 207-210 4 p. 4545459. (Proceedings - 20th Anniversary IEEE International SOC Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    8 Scopus citations
  • 2006

    2-level FIFO architecture design for switch fabrics in network-on-chip

    Huang, P.-T. & Hwang, W., 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 4863-4866 4 p. 1693720. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    15 Scopus citations

  • A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder

    Su, W. L., Chiueh, H.-M., Huang, P.-T. & Hwnag, W., 1 Dec 2006, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. p. 553-556 4 p. 4263426. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    2 Scopus citations

  • Low power pre-comparison scheme for NOR-Type 10T content addressable memory

    Huang, P.-T., Chang, W. K. & Hwang, W., 1 Dec 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. p. 1301-1304 4 p. 4145639. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    2 Scopus citations

  • On-chip DC-DC converter with frequency detector for dynamic voltage scaling technology

    Yang, J. W., Huang, P.-T. & Hwang, W., 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. p. 666-669 4 p. 4145481. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    3 Scopus citations
  • 2004

    Low power encoding schemes for run-time on-chip bus

    Huang, P.-T. & Hwang, W., Dec 2004, p. 1025-1028. 4 p.

    Research output: Contribution to conference › Paper › peer-review

    3 Scopus citations