Projects per year
Personal profile
Research Interests
Digital IC design, memory circuits and memory sub-system design, hardware design for AI and machine learning acceleration, 3D-IC design (Monolithic 3D-IC & TSV 3D-IC)
Education/Academic qualification
PhD, Electronics Engineering, National Yang Ming Chiao Tung University
External positions
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Collaborations and top research areas from the last five years
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Projects
- 8 Finished
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Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
Huang, P.-T. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫--111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-近記憶體運算及記憶體內運算電路設計
Huang, P.-T. (PI)
1/04/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
Huang, P.-T. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫--110年度智慧晶片系統與應用跨校教學聯盟-模組教材發展計畫-近記憶體運算及記憶體內運算電路設計
Huang, P.-T. (PI)
1/07/21 → 31/03/22
Project: Government Ministry › Ministry of Education(Include School)
-
Accuracy-Aware Deep Neural Network with Computation-in-Memory and 3D-Memory Circuits
Huang, P.-T. (PI)
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
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Continuous single-crystal germanium films using elevated-laser-liquid-phase-epitaxy technique for monolithic 3D integration
Pan, Y. M., Chiu, H. Y., Lin, N. C., Chung, H. T., Wang, C. Y., Chen, C. L., Shih, B. J., Yang, C. C., Huang, P. T., Shen, C. H., Sung, P. J., Wu, W. F., Chen, K. N. & Hu, C., 1 Apr 2025, In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 64, 4, 04SP56.Research output: Contribution to journal › Article › peer-review
Open Access -
Surface characteristics optimization during wafer-level backside silicon removal for SOI wafers in 3D integration
Shih, B. J., Chen, Z. Y., Chang, S. P., Chen, T. Y., Sung, P. J., Lin, N. C., Yang, C. C., Huang, P. T., Cheng, H. C., Li, M. Y., Radu, I. P. & Chen, K. N., 15 Apr 2025, In: Applied Surface Science. 688, 162366.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi
Shih, B. J., Pan, Y. M., Chung, H. T., Lee, C. L., Hsieh, I. C., Lin, N. C., Yang, C. C., Huang, P. T., Chen, H. M., Wang, C. Y., Chiu, H. Y., Cheng, H. C., Shen, C. H., Wu, W. F., Hou, T. H., Chen, K. N. & Hu, C., 2024, 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block
Lin, C. C., Lu, W., Huang, P. T. & Chen, H. M., 2024, 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 80-84 5 p. (2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning
Lu, W., Pei, H. H., Yu, J. R., Chen, H. M. & Huang, P. T., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review