Skip to main navigation
Skip to search
Skip to main content
National Yang Ming Chiao Tung University Academic Hub Home
English
中文
Home
Profiles
Research units
Research output
Projects
Prizes
Activities
Equipment
Impacts
Search by expertise, name or affiliation
View Scopus Profile
Pin Su
Professor
Institute of Electronics
Center for Semiconductor Technology Research
https://orcid.org/0000-0002-8213-4103
h-index
h10-index
h5-index
2275
Citations
25
h-index
Calculated based on number of publications stored in Pure and citations from Scopus
830
Citations
16
h-index
Calculated based on number of publications stored in Pure and citations from Scopus
269
Citations
9
h-index
Calculated based on number of publications stored in Pure and citations from Scopus
1994 …
2024
Research activity per year
Overview
Fingerprint
Network
Projects
(20)
Research output
(253)
Similar Profiles
(6)
Fingerprint
Dive into the research topics where Pin Su is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Keyphrases
6T SRAM Cell
20%
Analytical Solution
15%
Antiferroelectric
11%
Carbon Nanotube Field Effect Transistor (CNTFET)
35%
Cell Stability
10%
Drain Current
10%
Electrostatic Integrity
14%
Ferroelectric Field-effect Transistor (FeFET)
26%
FET Devices
10%
Fin Field-effect Transistor (FinFET)
47%
FinFET Devices
16%
Germanium-on-insulator (GeOI)
34%
Heteromeric Channel
10%
Impact Ionization
9%
Induced Variability
10%
InGaAs
15%
Line Edge Roughness
17%
Logic Circuit
30%
Monolithic 3-D (M3-D)
13%
MOSFET
52%
Negative Capacitance
13%
NMOSFET
15%
Non-volatile Memory
11%
NWFET
10%
PMOSFET
24%
Process Variation
11%
Quantum Confinement
13%
Quantum Confinement Effect
9%
Random Telegraph Noise
12%
Read Static Noise Margin
12%
Self-heating
9%
Short Channel
15%
Short Channel Effects
10%
Silicon-on-insulator
12%
SOI MOSFET
16%
SRAM Cell
34%
Strained Devices
12%
Subthreshold
13%
Subthreshold SRAM
15%
Subthreshold Swing
14%
Temperature Effect
19%
TFET SRAMs
16%
Threshold Voltage
16%
Transition Metal Dichalcogenides
12%
Tri-gate
11%
Tunnel FET
17%
Ultra-thin Body
41%
Ultra-thin SOI
11%
Uniaxial
15%
Work Function Variation
17%
Engineering
Access Time
8%
Atomistic Simulation
7%
Axial Strain
13%
Body Effect
8%
Carrier Mobility
5%
Channel Length
6%
Circuit Design
5%
Circuit Simulation
9%
Current Drain
15%
Dielectrics
10%
Dopants
5%
Edge Roughness
22%
Electric Field
5%
Field Effect Transistor
49%
Field-Effect Transistor
17%
Fin Width
5%
Floating Body
7%
Frequency Noise
11%
Gate Bias
6%
Gate Dielectric
5%
Gate Length
10%
Gate Voltage
6%
Impact Ionization
9%
Indium Gallium Arsenide
25%
Interlayer
13%
Inverter
9%
Isolation Method
7%
Logic Circuit
27%
Lookup Table
5%
Metal-Oxide-Semiconductor Field-Effect Transistor
100%
Mixed Mode
12%
Nanoscale
18%
Nanowire
5%
Noise Margin
22%
Nonvolatile Memory
10%
Operating Cell
5%
Process Variation
10%
Quantum Confinement
16%
Quantum Confinement Effect
11%
Radio Frequency
5%
Random Access Memory
8%
Random Variation
5%
Sense Amplifier
7%
Silicon on Insulator
16%
Simulation Result
6%
SPICE
7%
Temperature Dependence
14%
Tunnel
10%
Tunnel Construction
24%