Projects per year
Personal profile
Research Interests
Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices
Experience
Education/Academic qualification
PhD, Electrical Engineering and Computer Sciences, University of California, Berkeley
External positions
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Collaborations and top research areas from the last five years
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Projects
- 20 Finished
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
Su, P. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理,低能耗邏輯與記憶體元件及其高效能運算(2/2)
Su, P. (PI)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
Su, P. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Key Technologies of Ferroelectric FETs for Sub-Nanometer Nodes: Ferroelectric-Antiferroelectric Materials and Physics, Logic, Memory and Computation with Energy Efficiency
Su, P. (PI)
1/05/21 → 30/04/22
Project: Government Ministry › Other Government Ministry Institute
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Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
Su, P. (PI)
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
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Enabling Broader Memory Windows by Double-Gate Nanosheet Ferroelectric FETs for Next-Generation Non-Volatile Memory Storage
Wu, F., Chiu, C. Y., Lin, T. Y., Wu, C. H., Hu, V. P. H., Su, P. & Su, C. J., 2025, 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025. Institute of Electrical and Electronics Engineers Inc., (9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Enhancing Analog Performance in Ferroelectric Synapses via Independent Double-Gate Nanosheet FeFETs
Wu, F., Chiu, C. Y., Wu, C. H., Hu, V. P. H., Su, P. & Su, C. J., 2025, 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)
Semwal, S. & Su, P., 2025, In: IEEE Journal of the Electron Devices Society. 13, p. 154-160 7 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations -
Leveraging Ferroelectric Negative-Capacitance Effect for Energy Efficient Electronics
Dai, J. N. & Su, P., 2025, 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025. Institute of Electrical and Electronics Engineers Inc., (9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Modeling and Characterization of Polarization Switching for Ferroelectric HZO Considering Domain Propagation Effect
Lee, P. Y., Hsiang, K. Y., Chen, G. H., Tsai, H. T., Hung Lee, M. & Su, P., 2025, In: IEEE Transactions on Electron Devices. 72, 5, p. 2341-2346 6 p.Research output: Contribution to journal › Article › peer-review