Projects per year
Personal profile
Research Interests
Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices
Experience
Education/Academic qualification
PhD, University of California, Berkeley
External positions
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Dive into the research topics where Pin Su is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Network
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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Evaluation of Logic Circuits and SRAMs with 2D Negative-Capacitance FETs
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
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Modeling and Design Space Exploration for Negative-Capacitance FETs with 2D-Material Channel
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
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Comparison of 2-T FeFET nonvolatile memory cells: Gate select vs. drain select
Huang, B. K., You, W. X. & Su, P., 19 Apr 2021, VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 9440073. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories
Liu, Y. S. & Su, P., Apr 2021, In: IEEE Transactions on Electron Devices. 68, 4, p. 1639-1643 5 p.Research output: Contribution to journal › Article › peer-review
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Suppressed source-to-drain tunneling and short-channel effects for MFIS-type InGaAs and Si negative-capacitance FinFETs
Huang, S. E. & Su, P., 19 Apr 2021, VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 9440110. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A New 8T Hybrid Nonvolatile SRAM with Ferroelectric FET
You, W. X., Su, P. & Hu, C., 7 Feb 2020, In: IEEE Journal of the Electron Devices Society. 8, 1, p. 171-175 5 p., 8986584.Research output: Contribution to journal › Article › peer-review
Open Access -
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
Huang, S. E., Lin, S. H. & Su, P., 14 Jan 2020, In: IEEE Journal of the Electron Devices Society. 8, p. 105-109 5 p., 8959139.Research output: Contribution to journal › Article › peer-review
Open Access