Projects per year
Personal profile
Research Interests
Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices
Experience
Education/Academic qualification
PhD, Electrical Engineering and Computer Sciences, University of California, Berkeley
External positions
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Dive into the research topics where Pin Su is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理,低能耗邏輯與記憶體元件及其高效能運算(2/2)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Key Technologies of Ferroelectric FETs for Sub-Nanometer Nodes: Ferroelectric-Antiferroelectric Materials and Physics, Logic, Memory and Computation with Energy Efficiency
1/05/21 → 30/04/22
Project: Government Ministry › Other Government Ministry Institute
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Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
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A Tall Gate Stem GaN HEMT with Improved Power Density and Efficiency at Ka-Band
Lee, P. H., Lin, Y. C., Hsu, H. T., Tsao, Y. F., Dee, C. F., Su, P. & Chang, E. Y., 2023, (Accepted/In press) In: IEEE Journal of the Electron Devices Society. p. 1 1 p.Research output: Contribution to journal › Article › peer-review
Open Access -
An Alternative Way for Reconfigurable Logic-in-Memory with Ferroelectric FET
You, W. X., Huang, B. K. & Su, P., 1 Jan 2022, In: IEEE Transactions on Electron Devices. 69, 1, p. 444-446 3 p.Research output: Contribution to journal › Article › peer-review
4 Scopus citations -
Comparison of 2-D MoS2and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability
Liu, Y. S. & Su, P., 1 May 2022, In: IEEE Transactions on Electron Devices. 69, 5, p. 2738-2740 3 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
Design Space Exploration for Scaled FeFET Nonvolatile Memories: High-k Spacer as a Powerful Aid
Liu, Y. S., Huang, Y. Y. & Su, P., 2022, 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022. Institute of Electrical and Electronics Engineers Inc., p. 70-72 3 p. (6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers
Liu, Y. S. & Su, P., 2022, In: IEEE Journal of the Electron Devices Society. 10, p. 346-350 5 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Scopus citations