Projects per year
Personal profile
Research Interests
Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices
Experience
Education/Academic qualification
PhD, Electrical Engineering and Computer Sciences, University of California, Berkeley
External positions
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Collaborations and top research areas from the last five years
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Projects
- 20 Finished
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
Su, P. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理,低能耗邏輯與記憶體元件及其高效能運算(2/2)
Su, P. (PI)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
Su, P. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Key Technologies of Ferroelectric FETs for Sub-Nanometer Nodes: Ferroelectric-Antiferroelectric Materials and Physics, Logic, Memory and Computation with Energy Efficiency
Su, P. (PI)
1/05/21 → 30/04/22
Project: Government Ministry › Other Government Ministry Institute
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Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
Su, P. (PI)
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
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Analysis and Design of FeFET Synapse with Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications
Lin, H. L. & Su, P., 2024, In: IEEE Open Journal of Nanotechnology. 5, p. 17-22 6 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Super-Lamination HZO/ZrO2/HZO of Ferroelectric Memcapacitors with Morphotropic Phase Boundary (MPB) for High Capacitive Ratio and Non-Destructive Readout
Lou, Z. F., Chen, B. R., Hsiang, K. Y., Chang, Y. T., Liu, C. H., Tseng, H. C., Liao, H. T., Su, P. & Lee, M. H., 2024, In: Ieee Electron Device Letters. 45, 12, p. 2355-2358 4 p.Research output: Contribution to journal › Article › peer-review
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Unleashing Endurance Limits of Emerging Memory: Multi-Level FeRAM Recovery Array Empowered by a Coordinated Inverting Amplifier Circuit
Hsiang, K. Y., Chang, F. S., Lou, Z. F., Aich, A., Senapati, A., Lee, J. Y., Li, Z. X., Chen, J. H., Liu, C. H., Liu, C. W., Maikap, S., Su, P., Hou, T. H. & Lee, M. H., 1 Apr 2024, In: IEEE Transactions on Electron Devices. 71, 4, p. 2708-2713 6 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
Analysis and Design of Stacked-Nanosheet FeFET Synapse Conductance Response under Identical Pulse Scheme for Neuromorphic Applications
Lin, H. L. & Su, P., 2023, 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc., (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
A New Approach for Reconfigurable Multifunction Logic-in-Memory Using Complementary Ferroelectric-FET (CFeFET)
Huang, Y. Y., Huang, P. T., Lee, P. Y. & Su, P., 1 Aug 2023, In: IEEE Transactions on Electron Devices. 70, 8, p. 4497-4500 4 p.Research output: Contribution to journal › Article › peer-review
3 Scopus citations