Projects per year
Personal profile
Research Interests
Silicon-based Nanoelectronics, Compact Modeling for Circuit Simulation, Semiconductor Physics and Devices
Experience
Education/Academic qualification
PhD, University of California, Berkeley
External positions
Fingerprint
Dive into the research topics where Pin Su is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Network
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
-
次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理,低能耗邏輯與記憶體元件及其高效能運算(2/2)
1/05/22 → 30/04/23
Project: Government Ministry › Ministry of Science and Technology
-
Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
-
Evaluation and Analysis of 2D FeFET Synapse for Neuromorphic Computing
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
-
Key Technologies of Ferroelectric FETs for Sub-Nanometer Nodes: Ferroelectric-Antiferroelectric Materials and Physics, Logic, Memory and Computation with Energy Efficiency
1/05/21 → 30/04/22
Project: Government Ministry › Ministry of Science and Technology
-
Investigation and Modeling for 2D-FeFET based Nonvolatile Memory
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
-
Mitigating DIBL and Short-Channel Effects for III-V FinFETs with Negative-Capacitance Effects
Huang, S. E., You, W. X. & Su, P., 2022, In: IEEE Journal of the Electron Devices Society. 10, p. 65-71 7 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Comparison of 2-T FeFET nonvolatile memory cells: Gate select vs. drain select
Huang, B. K., You, W. X. & Su, P., 19 Apr 2021, VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 9440073. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories
Liu, Y. S. & Su, P., Apr 2021, In: IEEE Transactions on Electron Devices. 68, 4, p. 1639-1643 5 p.Research output: Contribution to journal › Article › peer-review
3 Scopus citations -
S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET
Huang, S. E., Su, P. & Hu, C-M., Sep 2021, In: IEEE Transactions on Electron Devices. 68, 9, p. 4787-4792 6 p., 9502416.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
Superior Immunity to Trapped-Charge induced Variability in 2D FeFET NVMs
Liu, Y. S. & Su, P., 2021, 2021 Silicon Nanoelectronics Workshop, SNW 2021. Institute of Electrical and Electronics Engineers Inc., (2021 Silicon Nanoelectronics Workshop, SNW 2021).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations