Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
1991 …2024

Research activity per year

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  • 2015

    Active ESD protection for input transistors in a 40-nm CMOS process

    Altolaguirre, F. A. & Ker, M.-D., 28 May 2015, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114533. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits

    Tsai, H. W. & Ker, M.-D., 16 Oct 2015, 2015 European Conference on Circuit Theory and Design, ECCTD 2015. Institute of Electrical and Electronics Engineers Inc., 7300129. (2015 European Conference on Circuit Theory and Design, ECCTD 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • ESD protection design with latchup-free immunity in 120V SOI process

    Huang, Y. J., Ker, M.-D., Huang, Y. J., Tsai, C. C., Jou, Y. N. & Lin, G. L., 20 Nov 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 7333481. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

    Liao, S. F., Tang, K. N., Ker, M.-D., Yeh, J. R., Chiou, H. C., Huang, Y. J., Tsai, C. C., Jou, Y. N. & Lin, G. L., 16 Oct 2015, 2015 European Conference on Circuit Theory and Design, ECCTD 2015. Institute of Electrical and Electronics Engineers Inc., 7300108. (2015 European Conference on Circuit Theory and Design, ECCTD 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Improve latch-up immunity by circuit solution

    Tsai, H. W. & Ker, M.-D., 25 Aug 2015, Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., p. 527-530 4 p. 7224450. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; vol. 2015-August).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

    Tang, K. N., Liao, S. F., Ker, M.-D., Chiou, H. C., Huang, Y. J., Tsai, C. C., Jou, Y. N. & Lin, G. L., 3 Aug 2015, 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015. Institute of Electrical and Electronics Engineers Inc., p. 325-328 4 p. 7175270. (2015 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    5 Scopus citations
  • Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

    Lin, C. Y., Chang, P. H., Chang, R. K., Ker, M.-D. & Wang, W. T., 25 Aug 2015, Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., p. 255-258 4 p. 7224380. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; vol. 2015-August).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • 2014

    A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

    Lin, K. Y., Ker, M.-D. & Lin, C. Y., 1 Jan 2014, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 237-240 4 p. 6865109. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • ESD protection design for wideband RF applications in 65-nm CMOS process

    Chu, L. W., Lin, C. Y., Ker, M.-D., Song, M. H., Tseng, J. C., Jou, C. P. & Tsai, M. H., 1 Jan 2014, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1480-1483 4 p. 6865426. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate

    Chen, S. H., Linten, D., Scholz, M., Hellings, G., Boschke, R., Groeseneken, G., Huang, Y. C. & Ker, M.-D., 1 Jan 2014, 2014 IEEE International Reliability Physics Symposium, IRPS 2014. Institute of Electrical and Electronics Engineers Inc., 6860651. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS

    Lin, C. Y., Fan, M. L., Ker, M.-D., Chu, L. W., Tseng, J. C. & Song, M. H., 2014, 2014 IEEE International Reliability Physics Symposium, IRPS 2014. Institute of Electrical and Electronics Engineers Inc., p. EL.1.1-EL.1.4 6861132. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    13 Scopus citations
  • Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process

    Altolaguirre, F. A. & Ker, M.-D., 23 Sep 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 250-253 4 p. 6908399. (Midwest Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Study on ESD protection design with stacked low-voltage devices for high-voltage applications

    Dai, C. T. & Ker, M.-D., 1 Jan 2014, 2014 IEEE International Reliability Physics Symposium, IRPS 2014. Institute of Electrical and Electronics Engineers Inc., 6861136. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    11 Scopus citations
  • 2013

    A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control

    Chen, W. M., Chiueh, H.-M., Chen, T. J., Ho, C. L., Jeng, C., Chang, S. T., Ker, M.-D., Lin, C. Y., Huang, Y. C., Chou, C. W., Fan, T. Y., Cheng, M. S., Liang, S. F., Chien, T. C., Wu, S. Y., Wang, Y. L., Shaw, F. Z., Huang, Y. H., Yang, C. H. & Chiou, J.-C. & 3 others, Chang, C. W., Chou, L. C. & Wu, C.-Y., 2013, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 286-287 2 p. 6487737. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 56).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    49 Scopus citations
  • Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

    Tsai, H. W., Ker, M.-D., Liu, Y. S. & Chuang, M. N., 15 Aug 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533803. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

    Yeh, C. T. & Ker, M.-D., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533801. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology

    Chiu, P. Y. & Ker, M.-D., 2013, Proceedings - IEEE 26th International SOC Conference, SOCC 2013. IEEE Computer Society, p. 33-36 4 p. 6749656. (International System on Chip Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

    Lin, C. Y., Chu, L. W., Tsai, S. Y., Ker, M.-D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., Wei, Y. L. & Chang, T. H., 2013, 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013. p. 241-244 4 p. 6720810. (Proceedings of the IEEE Conference on Nanotechnology).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • ESD-transient detection circuit with equivalent capacitance-coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology

    Yeh, C. T. & Ker, M.-D., 10 Sep 2013, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2013. 7 p. 6635907. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

    Dai, C. T. & Ker, M.-D., 9 Aug 2013, 2013 IEEE International Conference on Microelectronic Test Structures, ICMTS 2013 - Conference Proceedings. p. 127-130 4 p. 6528158. (IEEE International Conference on Microelectronic Test Structures).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    8 Scopus citations
  • Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

    Altolaguirre, F. A. & Ker, M.-D., 2013, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 2638-2641 4 p. 6572420. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

    Ker, M.-D. & Lin, C. Y., 2013, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 6628166. (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process

    Yeh, C. T. & Ker, M.-D., 7 Aug 2013, 2013 IEEE International Reliability Physics Symposium, IRPS 2013. 6532071. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • SCR device for on-chip ESD protection in RF power amplifier

    Lin, C. Y. & Ker, M.-D., 23 Dec 2013, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 6628124. (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

    Altolaguirre, F. A. & Ker, M.-D., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533866. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • 2012

    A 56-67 GHz low-noise amplifier with 5.1-dB NF and 2.5-kV HBM ESD protection in 65-nm CMOS

    Tsai, M. H., Hsieh, H. H., Lin, C. Y., Chu, L. W., Hsu, S. S. H., Jin, J. D., Yeh, T. J., Jou, C. P., Hsueh, F. L. & Ker, M.-D., 1 Dec 2012, 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings. p. 747-749 3 p. 6421722. (Asia-Pacific Microwave Conference Proceedings, APMC).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Design of AC-coupled circuit for high-speed interconnects

    Huang, C. W., Liu, K. J., Huang, Y. J., Chen, M. K., Lin, Y. L. & Ker, M.-D., 1 Dec 2012, 2012 IEEE Global High Tech Congress on Electronics, GHTCE 2012. p. 87-90 4 p. 6490130. (2012 IEEE Global High Tech Congress on Electronics, GHTCE 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process

    Chu, L. W., Lin, C. Y., Tsai, S. Y., Ker, M.-D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., Chang, T. H. & Wei, Y. L., 27 Nov 2012, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, EOS/ESD 2012. 6333325. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Design of ESD protection for RF CMOS power amplifier with inductor in matching network

    Tsai, S. Y., Lin, C. Y., Chu, L. W. & Ker, M.-D., 1 Dec 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 467-470 4 p. 6419073. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Design of negative high voltage generator for biphasic stimulator with soc integration consideration

    Huang, Y. C., Ker, M.-D. & Lin, C. Y., 1 Dec 2012, 2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications. p. 29-32 4 p. 6418477. (2012 IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Electronics and Systems for Better Life and Better Environment, BioCAS 2012 - Conference Publications).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    15 Scopus citations
  • ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process

    Lin, C. Y., Chu, L. W., Ker, M.-D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F. & Chang, T. H., 2012, 2012 IEEE International Reliability Physics Symposium, IRPS 2012. p. EL.3.1-EL.3.5 6241893. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

    Dai, C. T., Chiu, P. Y., Ker, M.-D., Tsai, F. Y., Peng, Y. H. & Tsai, C. K., 19 Nov 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012. 6306283. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-μm CMOS process

    Lin, C. Y., Li, Y. J. & Ker, M.-D., 7 Nov 2012, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. p. 125-128 4 p. 6328972. (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    9 Scopus citations
  • New design of transient-noise detection circuit with SCR device for system-level ESD protection

    Ker, M.-D. & Lin, W. Y., 7 Nov 2012, 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. p. 81-84 4 p. 6328961. (2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

    Yeh, C. T. & Ker, M.-D., 25 Jul 2012, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212606. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • 2011

    Adaptable stimulus driver for epileptic seizure suppression

    Ker, M.-D., Chen, W. L. & Lin, C. Y., 2011, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. 5783233. (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Design and implementation of capacitive sensor readout circuit on glass substrate for touch panel applications

    Wang, T. M. & Ker, M.-D., 28 Jun 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 269-272 4 p. 5783627. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations
  • Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

    Chiu, P. Y. & Ker, M.-D., 24 Jun 2011, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. 5783185. (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    10 Scopus citations
  • Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

    Yeh, C. T., Liang, Y. C. & Ker, M.-D., 2011, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. p. 1403-1406 4 p. 5937835. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems

    Ker, M.-D., 2011, 2011 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2011. 6117567. (2011 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations
  • ESD protection consideration in nanoscale CMOS technology

    Ker, M.-D. & Lin, C. Y., 1 Dec 2011, 2011 11th IEEE International Conference on Nanotechnology, NANO 2011. p. 720-723 4 p. 6144345. (Proceedings of the IEEE Conference on Nanotechnology).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

    Ker, M.-D., Lin, C. Y. & Tang-Long Chang, C., 2011, 2011 International Reliability Physics Symposium, IRPS 2011. p. EL.2.1-EL.2.2 5784565. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

    Ker, M.-D., Lin, C. Y. & Chang, T. L., 28 Jun 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 374-377 4 p. 5783551. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    8 Scopus citations
  • Modified LC-tank ESD protection design for 60-GHz RF applications

    Lin, C. Y., Chu, L. W., Tsai, S. Y., Ker, M.-D., Lu, T. H., Hsu, T. L., Hung, P. F., Song, M. H., Tseng, J. C., Chang, T. H. & Tsai, M. H., 2011, 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011. p. 57-60 4 p. 6043589. (2011 20th European Conference on Circuit Theory and Design, ECCTD 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations
  • New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels

    Yen, C. C., Lin, W. Y., Ker, M.-D., Yang, C. M., Chen, S. F. & Chen, T. Y., 31 Aug 2011, 6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'11 - Technical Program. 5941441. (6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'11 - Technical Program).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

    Altolaguirre, F. A. & Ker, M.-D., 5 Oct 2011, 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011. p. 108-112 5 p. 6021283. (2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

    Yeh, C. T., Liang, Y. C. & Ker, M.-D., 10 Nov 2011, Electrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011. 6045635. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    4 Scopus citations
  • Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design

    Yen, C. C., Lin, W. Y., Ker, M.-D., Tsai, C. L., Chen, S. F. & Chen, T. Y., 24 Jun 2011, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. 5783183. (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations
  • 2010

    2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

    Lin, C. Y. & Ker, M.-D., 31 Aug 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 3417-3420 4 p. 5537864. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations
  • A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology

    Wen, Y. R., Ker, M.-D. & Chen, W. Y., 20 Oct 2010, 2010 IEEE International Reliability Physics Symposium, IRPS 2010. p. 857-860 4 p. 5488718. (IEEE International Reliability Physics Symposium Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations