Projects per year
Personal profile
Research Interests
VLSI Testing, Statistical Timing Analysis, Physical Design Automation, Test Compression/Compaction
Experience
Education/Academic qualification
PhD, University of California, Santa Barbara
External positions
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Machine-Learning Techniques and ATPG Methodologies for Reducing DPPM
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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降低客退率之機器學習技術與自動化測試向量產生方法(II)
1/08/24 → 31/07/25
Project: Government Ministry › Ministry of Science and Technology
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基於強化學習之多層障礙物排除直角史坦納最小樹繞線器
1/08/23 → 31/07/24
Project: Government Ministry › Ministry of Science and Technology
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降低客退率之機器學習技術與自動化測試向量產生方法(II)
1/08/23 → 31/07/24
Project: Government Ministry › Ministry of Science and Technology
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基於強化學習之多層障礙物排除直角史坦納最小樹繞線器
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
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Improving Cell-Aware Test for Intra-Cell Short Defects
Lee, D. Z., Chen, Y. Y., Wu, K. C. & Chao, M. C. T., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 436-441 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Rule Generation for Classifying SLT Failed Parts
Hsu, H. C., Lu, C. C., Wang, S. W., Jones, K., Wu, K. C. & Chao, M. C. T., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; vol. 2022-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Test Methodology for Defect-Based Bridge Faults
Chang, S. W., Nien, Y. T., Hu, Y. P., Wu, K. C., Wang, C. C., Huang, F. S., Tang, Y. L., Chen, Y. C., Chen, M. C. & Chao, M. C. T., 2022, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.Research output: Contribution to journal › Article › peer-review
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Identifying good-dice-in-bad-neighborhoods using artificial neural networks
Yang, C. H., Yen, C. H., Wang, T. R., Chen, C. T., Chern, M., Chen, Y. Y., Lee, J. N., Kao, S. Y., Wu, K-C. & Chao, C-T., 25 Apr 2021, Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 9441055. (Proceedings of the IEEE VLSI Test Symposium; vol. 2021-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Y. T., Wu, K. C., Lee, D. Z., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, M. C. T., 2021, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review