Projects per year
Personal profile
Research Interests
Three-Dimensional Integrated Circuits, Heterogeneous Integration, Advanced Packaging Technologies
Experience
Education/Academic qualification
PhD, Electrical Engineering and Computer Science, Massachusetts Institute of Technology
External positions
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Collaborations and top research areas from the last five years
Projects
- 30 Finished
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Ultra-high Bandwidth Memory And Logic Chip Integration System Platform Realized By Ultra-thin Wafer Stacking With Bumpless Structure
Chen, K.-N. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Research and Development of Micro Electronics Division
Chen, K.-N. (PI)
1/01/23 → 31/12/23
Project: Government Ministry › Other Government Ministry Institute
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Ultra-high Bandwidth Memory And Logic Chip Integration System Platform Realized By Ultra-thin Wafer Stacking With Bumpless Structure
Chen, K.-N. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Low-Temperature Short-Duration Cu Hybrid Bonding Technology for 3D IC and Heterogeneous Integration
Chen, K.-N. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Research and Development of Micro Electronics Division
Chen, K.-N. (PI)
1/01/22 → 31/12/22
Project: Government Ministry › Other Government Ministry Institute
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Continuous single-crystal germanium films using elevated-laser-liquid-phase-epitaxy technique for monolithic 3D integration
Pan, Y. M., Chiu, H. Y., Lin, N. C., Chung, H. T., Wang, C. Y., Chen, C. L., Shih, B. J., Yang, C. C., Huang, P. T., Shen, C. H., Sung, P. J., Wu, W. F., Chen, K. N. & Hu, C., 1 Apr 2025, In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 64, 4, 04SP56.Research output: Contribution to journal › Article › peer-review
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Future novel memory device fabrication, heterogenous integration and packaging innovations
Gan, C. L., Huang, C. Y., Chen, K. N., Badwe, N. U. & Zhang, S., Jan 2025, In: Materials Science in Semiconductor Processing. 185, 108998.Research output: Contribution to journal › Editorial
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Low-temperature photo imageable dielectric for redistribution layers in advanced packaging application
Chang, S. P., Chuang, Z. I., Wu, Y. J., Ho, E. M., Huang, Y. C. & Chen, K. N., Feb 2025, In: Materials Science in Semiconductor Processing. 186, 109083.Research output: Contribution to journal › Article › peer-review
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Surface characteristics optimization during wafer-level backside silicon removal for SOI wafers in 3D integration
Shih, B. J., Chen, Z. Y., Chang, S. P., Chen, T. Y., Sung, P. J., Lin, N. C., Yang, C. C., Huang, P. T., Cheng, H. C., Li, M. Y., Radu, I. P. & Chen, K. N., 15 Apr 2025, In: Applied Surface Science. 688, 162366.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi
Shih, B. J., Pan, Y. M., Chung, H. T., Lee, C. L., Hsieh, I. C., Lin, N. C., Yang, C. C., Huang, P. T., Chen, H. M., Wang, C. Y., Chiu, H. Y., Cheng, H. C., Shen, C. H., Wu, W. F., Hou, T. H., Chen, K. N. & Hu, C., 2024, 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations
Prizes
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Excellent Young Electrical Engineer Award, Chinese Institute of Electrical Engineering
Chen, K.-N. (Recipient), 2012
Prize: Honorary award
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Activities
- 1 Invited talk
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IEEE Interconnect Technology Conference (IITC)
Chen, K.-N. (Speaker)
4 Jun 2018Activity: Talk or presentation › Invited talk