Projects per year
Personal profile
Research Interests
Three-Dimensional Integrated Circuits, Heterogeneous Integration, Advanced Packaging Technologies
Experience
Education/Academic qualification
PhD, Electrical Engineering and Computer Science, Massachusetts Institute of Technology
External positions
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Dive into the research topics where Kuan-Neng Chen is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 30 Finished
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Ultra-high Bandwidth Memory And Logic Chip Integration System Platform Realized By Ultra-thin Wafer Stacking With Bumpless Structure
Chen, K.-N. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Research and Development of Micro Electronics Division
Chen, K.-N. (PI)
1/01/23 → 31/12/23
Project: Government Ministry › Other Government Ministry Institute
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Low-Temperature Short-Duration Cu Hybrid Bonding Technology for 3D IC and Heterogeneous Integration
Chen, K.-N. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Ultra-high Bandwidth Memory And Logic Chip Integration System Platform Realized By Ultra-thin Wafer Stacking With Bumpless Structure
Chen, K.-N. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Research and Development of Micro Electronics Division
Chen, K.-N. (PI)
1/01/22 → 31/12/22
Project: Government Ministry › Other Government Ministry Institute
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Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs
Shih, B. J., Pan, Y. M., Chung, H. T., Lin, N. C., Yang, C. C., Huang, P. T., Cheng, H. C., Shen, C. H., Shieh, J. M., Wu, W. F., Chen, K. N. & Hu, C., 1 Apr 2024, In: Japanese journal of applied physics. 63, 4, 04SP30.Research output: Contribution to journal › Article › peer-review
Open Access -
A Novel Low-Warpage Hyper RDL (HRDL) Interposer Enabled by Low Temperature Hybrid Bonding for Advanced Packaging Applications
Huang, Y. C., Lin, Y. X., Hsiung, C. K., Yang, Y. T., Hung, T. H. & Chen, K. N., 1 Mar 2024, In: Ieee Electron Device Letters. 45, 3, p. 452-455 4 p.Research output: Contribution to journal › Article › peer-review
2 Scopus citations -
Application of Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique on Different Oriented Wafers for Monolithic 3DIC Integration
Shih, B. J., Pan, Y. M., Wang, C. Y., Chiu, H. Y., Yang, C. C., Shen, C. H., Cheng, H. C. & Chen, K. N., 2024, Proceedings - IEEE 74th Electronic Components and Technology Conference, ECTC 2024. Institute of Electrical and Electronics Engineers Inc., p. 2167-2171 5 p. (Proceedings - Electronic Components and Technology Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Review on Hybrid Bonding Interconnection and Its Characterization
Hsiung, C. K. & Chen, K. N., 1 Apr 2024, In: IEEE Nanotechnology Magazine. 18, 2, p. 41-50 10 p.Research output: Contribution to journal › Article › peer-review
4 Scopus citations -
Comparison of Different Copper Nitride Passivation Layers Fabrication Methodology and Optimal Growth Condition for Low Temperature Copper-to-Copper Bonding in Advanced Packaging
Wang, C. Y., Hung, T. H., Liu, P. J. & Chen, K. N., 2024, Proceedings - IEEE 74th Electronic Components and Technology Conference, ECTC 2024. Institute of Electrical and Electronics Engineers Inc., p. 2157-2162 6 p. (Proceedings - Electronic Components and Technology Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Prizes
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Excellent Young Electrical Engineer Award, Chinese Institute of Electrical Engineering
Chen, K.-N. (Recipient), 2012
Prize: Honorary award
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Activities
- 1 Invited talk
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IEEE Interconnect Technology Conference (IITC)
Chen, K.-N. (Speaker)
4 Jun 2018Activity: Talk or presentation › Invited talk