Kai-Chiang Wu

Research output

Research output per year 2004 2019 2020 2021 2022 2023

• 32 Conference contribution
• 10 Article

Research output per year

Research output per year

Search results

• 2022

  Improving Cell-Aware Test for Intra-Cell Short Defects

  Lee, D. Z., Chen, Y. Y., Wu, K. C. & Chao, M. C. T., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 436-441 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Fault 100%
  • Defects 86%
  • Cell 63%
  • Coverage 23%
  • Polygon 21%
  2 Scopus citations

• Rule Generation for Classifying SLT Failed Parts

  Hsu, H. C., Lu, C. C., Wang, S. W., Jones, K., Wu, K. C. & Chao, M. C. T., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; vol. 2022-April).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Unsupervised learning 100%
  • Visibility 87%
  • Decision trees 85%
  • Integrated circuits 80%
  • Transistors 74%
• 2021

  An energy-efficient approximate systolic array based on timing error prediction and prevention

  Huang, N. C., Tseng, W. K., Chou, H. J. & Wu, K. C., 25 Apr 2021, Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 9441004. (Proceedings of the IEEE VLSI Test Symposium; vol. 2021-April).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Systolic arrays 100%
  • Deep neural networks 75%
  • Image classification 27%
  • Energy efficiency 20%
  • Machine learning 18%

• FOX-NAS: Fast, On-device and Explainable Neural Architecture Search

  Liu, C. H., Han, Y. S., Sung, Y. Y., Lee, Y., Chiang, H. Y. & Wu, K. C., 2021, Proceedings - 2021 IEEE/CVF International Conference on Computer Vision Workshops, ICCVW 2021. Institute of Electrical and Electronics Engineers Inc., p. 789-797 9 p. (Proceedings of the IEEE International Conference on Computer Vision; vol. 2021-October).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Neural networks 100%
  • Simulated annealing 82%
  • Network architecture 77%
  • Program processors 69%
  • Computer hardware 48%

• Identifying good-dice-in-bad-neighborhoods using artificial neural networks

  Yang, C. H., Yen, C. H., Wang, T. R., Chen, C. T., Chern, M., Chen, Y. Y., Lee, J. N., Kao, S. Y., Wu, K-C. & Chao, C-T., 25 Apr 2021, Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 9441055. (Proceedings of the IEEE VLSI Test Symposium; vol. 2021-April).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Neural networks 100%
  • Defects 75%
  • Linear regression 55%
  • Costs 20%
  • Experiments 19%

• ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

  Liu, S., Kuo, J. H., Tang, L., Huang, N. C., Tsai, D. Y., Yang, M. H. & Wu, K. C., 19 Apr 2021, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9427328. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • compilers 100%
  • artificial intelligence 95%
  • RRAM 92%
  • Artificial intelligence 57%
  • chips 52%
  1 Scopus citations

• The 2020 Low-Power Computer Vision Challenge

  Hu, X., Chang, M. C., Chen, Y., Sridhar, R., Hu, Z., Xue, Y., Wu, Z., Pi, P., Shen, J., Tan, J., Lian, X., Liu, J., Wang, Z., Liu, C. H., Han, Y. S., Sung, Y. Y., Lee, Y., Wu, K. C., Guo, W. X., Lee, R., & 14 othersLiang, S., Wang, Z., Ding, G., Zhang, G., Xi, T., Chen, Y., Cai, H., Zhu, L., Zhang, Z., Han, S., Jeong, S., Kwon, Y., Wang, T. & Pan, J., 6 Jun 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021. Institute of Electrical and Electronics Engineers Inc., 9458522. (2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Computer vision 100%
  • Drones 25%
  • Edge computing 24%
  • Cellular telephones 18%
  • Unmanned aerial vehicles (UAV) 18%
  1 Scopus citations
• 2020

  CNN-based Stochastic Regression for IDDQ Outlier Identification

  Chen, C. T., Yen, C. H., Wen, C. Y., Yang, C. H., Wu, K. C., Chern, M., Chen, Y. Y., Kuo, C. Y., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Apr 2020, Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 9107570. (Proceedings of the IEEE VLSI Test Symposium; vol. 2020-April).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Convolutional neural networks 100%
  • Testing 56%
  • Engineers 38%
  • Defects 37%
  2 Scopus citations

• Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator

  Liu, S. M., Tang, L., Huang, N. C., Tsai, D. Y., Yang, M. X. & Wu, K. C., 10 Aug 2020, 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p. 9196335. (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Particle accelerators 100%
  • Fault tolerance 97%
  • Deep learning 88%
  • Neural networks 59%
  • Static random access storage 43%
  6 Scopus citations

• Selective sensor placement for cost-effective online aging monitoring and resilience

  Chang, H. C., Huang, L. A., Wu, K. C. & Chen, Y. G., 20 Sep 2020, ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, p. 95-102 8 p. (Proceedings of the International Symposium on Physical Design).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Aging of materials 100%
  • Monitoring 70%
  • Sensors 63%
  • Costs 47%
  • Detectors 41%

• Test Methodology for Defect-based Bridge Faults

  Hu, Y. P., Chang, S. W., Wu, K. C., Wang, C. C., Huang, F. S., Tang, Y. L., Chen, Y. C., Chen, M. C. & Chao, M. C. T., Sep 2020, Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020. Institute of Electrical and Electronics Engineers Inc., p. 106-111 6 p. 9226574. (Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Defects 86%
  • Methodology 44%
  • Industrial Design 9%
  • SPICE 8%
  • Product design 7%
• 2019

  Aging-aware chip health prediction adopting an innovative monitoring strategy

  Wang, Y. T., Wu, K-C., Chou, C. H. & Chang, S. C., 21 Jan 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 179-184 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Aging of materials 100%
  • Health 91%
  • Monitoring 70%
  • Networks (circuits) 34%
  • Machine learning 22%
  5 Scopus citations

• Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs

  Huang, N. C., Chen, Y. G. & Wu, K. C., Jul 2019, Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. IEEE Computer Society, p. 218-223 6 p. 8839460. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; vol. 2019-July).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Networks (circuits) 100%
  • Timing circuits 93%
  • Electric power utilization 89%
  • Aging of materials 48%
  • Genetic algorithms 42%

• ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience

  Wu, K-C., Huang, W. T. & Huang, C. Y., Jul 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 263-268 6 p. 8854407. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Flip flop circuits 100%
  • Aging of materials 68%
  • Costs 32%
  • Degradation 29%
  • Networks (circuits) 11%

• Layout-Based Dual-Cell-Aware Tests

  Wu, T. W., Lee, D. Z., Wu, K-C., Huang, Y. H., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, C-T., 1 Apr 2019, 2019 IEEE 37th VLSI Test Symposium, VTS 2019. IEEE Computer Society, 8758646. (Proceedings of the IEEE VLSI Test Symposium; vol. 2019-April).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Defects 100%
  • SPICE 52%
  • System-on-chip 24%
  • Equivalent circuits 23%
  • Chemical activation 21%
  2 Scopus citations

• Methodology of generating timing-slack-based cell-aware tests

  Nien, Y. T., Wu, K. C., Lee, D. Z., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, M. C. T., Nov 2019, 2019 IEEE International Test Conference, ITC 2019. Institute of Electrical and Electronics Engineers Inc., 9000119. (Proceedings - International Test Conference; vol. 2019-November).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Timing 100%
  • Fault 82%
  • Cell 62%
  • Methodology 61%
  • Defects 57%
  1 Scopus citations

• Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications

  Huang, N. C., Chen, S. Y. & Wu, K-C., 14 May 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 692-697 6 p. 8714949. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Approximate Design 100%
  • Sensor 77%
  • Adders 72%
  • Learning 60%
  • Deep learning 59%
  9 Scopus citations
• 2018

  Lifetime Reliability Trojan Based on Exploring Malicious Aging

  Tseng, T. H., Li, S. C. & Wu, K-C., 6 Dec 2018, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 74-79 6 p. 8567414. (Proceedings of the Asian Test Symposium; vol. 2018-October).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Hardware security 100%
  • Aging of materials 62%
  • Malware 57%
  • Networks (circuits) 43%
  • Supply chains 25%

• MAUI: Making aging useful, intentionally

  Wu, K-C., Tseng, T. H. & Li, S. C., 19 Apr 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., p. 527-532 6 p. (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; vol. 2018-January).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Aging of materials 100%
  • Degradation 63%
  • Tolerance 43%
  • Clocks 35%
  • Performance 23%
  1 Scopus citations
• 2017

  Analysis and optimization of variable-latency designs in the presence of timing variability

  Tsai, C. L., Cheng, C. W., Huang, N. C. & Wu, K-C., 11 May 2017, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., p. 1219-1224 6 p. 7927174. (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Timing circuits 100%
  • Networks (circuits) 53%
  • Clocks 27%
  • Particle swarm optimization (PSO) 27%
  • Aging of materials 25%
  3 Scopus citations

• Fast WAT test structure for measuring VT variance based on latch-based comparators

  Lee, K. C., Wu, K-C., Tsai, C. Y. & Chao, C-T., 15 May 2017, Proceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017. IEEE Computer Society, 7928928. (Proceedings of the IEEE VLSI Test Symposium).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Threshold voltage 100%
  • Leakage currents 97%
  • Electric potential 93%
  • Experiments 32%
  2 Scopus citations

• Workload-aware lifetime Trojan based on statistical aging manipulation

  Tseng, T. H., Wang, S. S., Chen, J. Y. & Wu, K-C., 18 Oct 2017, 2017 IEEE Conference on Dependable and Secure Computing. Institute of Electrical and Electronics Engineers Inc., p. 159-165 7 p. 8073842. (2017 IEEE Conference on Dependable and Secure Computing).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Hardware security 100%
  • Aging of materials 62%
  • Malware 57%
  • Networks (circuits) 28%
  • Supply chains 25%
• 2012

  Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms

  Wu, K-C., Lee, M. C., Marculescu, D. & Chang, S. C., 24 May 2012, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. p. 1269-1274 6 p. 6176687. (Proceedings -Design, Automation and Test in Europe, DATE).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Negative bias temperature instability 100%
  • Electric breakdown 78%
  • Electromigration 59%
  • Time-to-failure 57%
  • Temperature 27%
  7 Scopus citations
• 2011

  Aging-aware timing analysis and optimization considering path sensitization

  Wu, K-C. & Marculescu, D., 31 May 2011, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. p. 1572-1577 6 p. 5763249. (Proceedings -Design, Automation and Test in Europe, DATE).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Aging of materials 100%
  • Delay circuits 57%
  • Degradation 29%
  • Networks (circuits) 22%
  • Oxides 17%
  17 Scopus citations

• Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

  Wu, K-C., Marculescu, D., Lee, M. C. & Chang, S. C., 19 Sep 2011, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 139-144 6 p. 5993626. (Proceedings of the International Symposium on Low Power Electronics and Design).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Negative bias temperature instability 100%
  • Degradation 48%
  • Aging of materials 44%
  • Sleep 44%
  • Networks (circuits) 38%
  11 Scopus citations
• 2010

  Clock skew scheduling for soft-error-tolerant sequential circuits

  Wu, K-C. & Marculescu, D., 9 Jun 2010, DATE 10 - Design, Automation and Test in Europe. p. 717-722 6 p. 5456956. (Proceedings -Design, Automation and Test in Europe, DATE).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Sequential circuits 100%
  • Clocks 65%
  • Scheduling 53%
  • Linear programming 28%
  • Integrated circuits 14%
  1 Scopus citations
• 2009

  Joint logic restructuring and pin reordering against NBTI-induced performance degradation

  Wu, K-C. & Marculescu, D., 22 Oct 2009, Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09. p. 75-80 6 p. 5090636. (Proceedings -Design, Automation and Test in Europe, DATE).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Negative bias temperature instability 100%
  • Degradation 48%
  • Transistors 29%
  • Oxides 9%
  • Aging of materials 9%
  51 Scopus citations
• 2008

  Power-aware soft error hardening via selective voltage scaling

  Wu, K-C. & Marculescu, D., 1 Dec 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 301-306 6 p. 4751877. (26th IEEE International Conference on Computer Design 2008, ICCD).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Voltage scaling 100%
  • Hardening 74%
  • Logic circuits 15%
  • Networks (circuits) 14%
  • Electric potential 13%
  18 Scopus citations

• Process variability-aware transient fault modeling and analysis

  Miskov-Zivanov, N., Wu, K-C. & Marculescu, D., 26 Dec 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008. p. 685-690 6 p. 4681651. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Digital circuits 100%
  • Transistors 76%
  • Electric potential 46%
  22 Scopus citations

• Soft error rate reduction using redundancy addition and removal

  Wu, K-C. & Marculescu, D., 21 Aug 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 559-564 6 p. 4484014. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Redundancy 100%
  • Logic circuits 33%
  • Radiation 23%
  • Degradation 20%
  • Data storage equipment 17%
  24 Scopus citations
• 2006

  Delay variation tolerance for domino circuits

  Wu, K-C., Hsieh, C. T. & Chang, S. C., 19 Sep 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 354-359 6 p. 1594708. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Networks (circuits) 100%
• 2004

  Re-synthesis for delay variation tolerance

  Chang, S. C., Hsieh, C. T. & Wu, K-C., 20 Sep 2004, 41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004. ACM, p. 814-819 6 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • Wire 100%
  • Defects 91%
  • Networks (circuits) 73%
  7 Scopus citations