Projects per year
Personal profile
Research Interests
AI computing platform design, approximate computing for AI applications, cybersecurity and hardware Trojan, SoC design automation
Experience
1.Software Engineer, Design Technology Solutions, Intel Corporation, 08/2011 – 07/2013
2.Research Assistant, Energy Aware Computing (EnyAC) Group, Carnegie Mellon University, 08/2006 – 07/2011
Education/Academic qualification
PhD, Electrical & Computer Engineering, Carnegie Mellon University
External positions
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Network
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Edge-deployment-aware Vision DNN Architecture and Module Design
1/05/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Edge-deployment-aware Vision DNN Architecture and Module Design
1/05/20 → 30/04/21
Project: Government Ministry › Other Government Ministry Institute
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Improving Cell-Aware Test for Intra-Cell Short Defects
Lee, D. Z., Chen, Y. Y., Wu, K. C. & Chao, M. C. T., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 436-441 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Scopus citations -
Rule Generation for Classifying SLT Failed Parts
Hsu, H. C., Lu, C. C., Wang, S. W., Jones, K., Wu, K. C. & Chao, M. C. T., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; vol. 2022-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Test Methodology for Defect-Based Bridge Faults
Chang, S. W., Nien, Y. T., Hu, Y. P., Wu, K. C., Wang, C. C., Huang, F. S., Tang, Y. L., Chen, Y. C., Chen, M. C. & Chao, M. C. T., 2022, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.Research output: Contribution to journal › Article › peer-review
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Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs
Huang, N. C., Cheng, C. W. & Wu, K. C., 1 Jan 2022, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30, 1, p. 81-94 14 p.Research output: Contribution to journal › Article › peer-review
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An energy-efficient approximate systolic array based on timing error prediction and prevention
Huang, N. C., Tseng, W. K., Chou, H. J. & Wu, K. C., 25 Apr 2021, Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 9441004. (Proceedings of the IEEE VLSI Test Symposium; vol. 2021-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Prizes
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Distinguished Mentor Award, National Chiao Tung University
Wu, Kai-Chiang (Recipient), 2015
Prize: Honorary award
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Distinguished Mentor Award, National Chiao Tung University
Wu, Kai-Chiang (Recipient), 2016
Prize: Honorary award
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