Projects per year
Personal profile
Research Interests
Nano Devices, RF CMOS Device Modeling, High Performance Analog Device Design, Non-volatile Memory Device Design & Reliability, SoC Integration Technology
Experience
Education/Academic qualification
PhD, National Chiao Tung University
External positions
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Dive into the research topics where Jyh-Chyurn Guo is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 13 Finished
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New Compact Models with Layout Dependent Parasitic Effects and Improvement Solutions for Low Power and Low Noise mm-wave Devices and Circuits Co-design
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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New Compact Models with Layout Dependent Parasitic Effects and Improvement Solutions for Low Power and Low Noise mm-wave Devices and Circuits Co-design
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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New Compact Models with Layout Dependent Parasitic Effects and Improvement Solutions for Low Power and Low Noise mm-wave Devices and Circuits Co-design
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
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A Comprehensive Characterization and Modeling of Layout Dependent Effects and 3-D Parasitics for RF Performance and Broadband Noise in Planar Bulk and Multi-Gate Nanoscale Devices
1/08/17 → 31/12/18
Project: Government Ministry › Ministry of Science and Technology
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A Comprehensive Characterization and Modeling of Layout Dependent Effects and 3-D Parasitics for RF Performance and Broadband Noise in Planar Bulk and Multi-Gate Nanoscale Devices
1/08/16 → 31/12/17
Project: Government Ministry › Ministry of Science and Technology
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SiC Strained nMOSFETs with Enhanced High- Frequency Performance and Impact on Flicker Noise and Random Telegraph Noise
Guo, J. C. & Chang, C. S., Jun 2020, In: IEEE Transactions on Microwave Theory and Techniques. 68, 6, p. 2259-2267 9 p., 9063679.Research output: Contribution to journal › Article › peer-review
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METHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICE
Guo, J-C., 9 Jul 2019, Patent No. US 10,345,371 B2Research output: Patent
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New observation and analysis of layout dependent effects in sub-40nm multi-ring and multi-finger nmosfets for high frequency applications
Li, Z. C., Guo, J. C. & Lin, J. M., Apr 2019, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804636. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs
Guo, J-C., Ou, J. R. & Lin, J. M., 1 Jun 2019, 2019 IEEE MTT-S International Microwave Symposium, IMS 2019. Institute of Electrical and Electronics Engineers Inc., p. 963-966 4 p. 8700891. (IEEE MTT-S International Microwave Symposium Digest; vol. 2019-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-Finger nMOSFETs
Guo, J-C. & Yeh, K. L., 16 Nov 2018, EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 146-149 4 p. 8539965. (EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Activities
- 1 Invited talk
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IMS 2013 MTT-14 workshop
Jyh-Chyurn Guo (Speaker)
1 Jun 2013Activity: Talk or presentation › Invited talk