俊達 黃

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Juinn-Dar Huang

Professor

 https://orcid.org/0000-0001-5961-7863
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
Calculated based on number of publications stored in Pure and citations from Scopus
1993 …2024

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  • 2007

    Fault dictionary size reduction for million-gate large circuits

    Hong, Y. R. & Huang, J.-D., 1 Dec 2007, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 829-834 6 p. 4196138. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    6 Scopus citations

  • Input selection encoding for low power multiplexer tree

    Chang, H. E., Huang, J.-D. & Chen, C. I., 28 Sep 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239445. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    8 Scopus citations

  • Low-power instruction cache architecture using pre-tag checking

    Cheng, S. Y. & Huang, J.-D., 28 Sep 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239408. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    1 Scopus citations

  • Microarchitecture-aware floorplanning for processor performance optimization

    Chen, C. Y., Huang, J.-D. & Chen, H.-M., 28 Sep 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239416. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

  • 2006

    A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

    Chen, C. H., Lee, G. W., Huang, J.-D. & Jou, J. Y., 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., p. 600-605 6 p. 1594751. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    21 Scopus citations

  • FSM-based transaction-level functional coverage for interface compliance verification

    Su, M. Y., Shih, C. H., Huang, J.-D. & Jou, J. Y., 19 Sep 2006, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 448-453 6 p. 1594726. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    6 Scopus citations
  • 2005

    Formal compliance verification of interface protocols

    Yang, Y. C., Huang, J.-D., Yen, C. C., Shih, C. H. & Jou, J. Y., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). p. 12-15 4 p. 1500007. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); vol. 2005).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    7 Scopus citations

  • Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

    Shih, C. H., Huang, J.-D. & Jou, J. Y., 2005, Proceedings - Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05. p. 87-93 7 p. 1568819. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    9 Scopus citations
  • 1998

    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis

    Jiang, J. H. R., Jou, J. Y. & Huang, J.-D., 1998, Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., p. 712-717 6 p. 724564. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    13 Scopus citations
  • 1993

    PLANE: A new ATPG system for PLAs

    Huang, J.-D. & Shen, W. Z., 1 Jan 1993, ATS 1993 Proceedings - 2nd Asian Test Symposium. IEEE Computer Society, p. 107-112 6 p. 398788. (Proceedings of the Asian Test Symposium).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    1 Scopus citations