Personal profile
Research Interests
Electronic Design Automation (EDA), Biochip Design Automation, Microprocessor Design, Silicon IP and SoC Design
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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Collaborations and top research areas from the last five years
Projects
- 25 Finished
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
Huang, J.-D. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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通用於深度學習之神經網路加速器晶片開發暨產業落地(1/4)
Huang, J.-D. (PI)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Edge-Intelligence-SOC Design and Verification Methodology Development
Huang, J.-D. (PI)
1/05/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Expertfuse: A huffman tree-based gradual expert integration framework for MoE models
Fang, Y. & Huang, J., Mar 2026, In: Neural Networks. 195, 108274.Research output: Contribution to journal › Article › peer-review
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An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning
Wu, J. E., Hu, T. W., Liang, C. Y. & Huang, J. D., 2025, ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations -
Codeword Decomposition and Recoding Based Lossless Model Compression Algorithm and Its VLSI Decompressor Design
Ho, L. M., Liang, C. Y. & Huang, J. D., 2025, AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., (AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications
Hsieh, M. H., Li, X. H., Huang, Y. H., Kuo, P. H. & Huang, J. D., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
4 Scopus citations -
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems
Chu, Y. D., Kuo, P. H., Ho, L. M. & Huang, J. D., 2024, 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 437-441 5 p. (2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review