Projects per year
Personal profile
Research Interests
Electronic Design Automation (EDA), Biochip Design Automation, Microprocessor Design, Silicon IP and SoC Design
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
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Dive into the research topics where Juinn-Dar Huang is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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通用於深度學習之神經網路加速器晶片開發暨產業落地(1/4)
1/05/22 → 30/04/23
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-子計畫三：針對邊緣運算最佳化之Transformer神經網路硬體加速器設計與實作
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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Edge-Intelligence-SOC Design and Verification Methodology Development
1/05/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability
Hu, C. H., Tseng, I. H., Kuo, P. H. & Huang, J. D., 2022, Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Institute of Electrical and Electronics Engineers Inc., p. 246-249 4 p. (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
Song, L. Y., Kuo, T. C., Wang, M. H., Liu, C. N. J. & Huang, J. D., 2022, ASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 80-85 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2022-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
Chou, W. C., Huang, C. W. & Huang, J. D., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
Fan, K. Y., Chen, J. H., Liu, C. N. & Huang, J. D., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing
Lin, W. C., Chang, Y. C. & Huang, J. D., 6 Jun 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021. Institute of Electrical and Electronics Engineers Inc., 9458511. (2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
2 Scopus citations