Keyphrases
Floorplanning
42%
Wirelength
37%
Routability
31%
Analog Layout
27%
Chip Package
21%
Bump
20%
IR Drop
19%
Circuit Performance
19%
Signal Integrity
18%
Design Flow
18%
Floor Plan Design
17%
Area Array
17%
Package Design
17%
Power Network
16%
Placer
16%
Low Power
16%
Design Cost
14%
Router
14%
Digital Microfluidic Biochips
14%
Voltage Islands
14%
Flip-chip Design
13%
Analog Placement
13%
Scan Chain
13%
Power Delivery
13%
Nanometre
12%
Test Power
12%
3D IC
12%
Layout Migration
12%
Power Supply Noise
12%
Routing Algorithm
12%
Analog Circuits
11%
Escape Routing
11%
Cyber-physical
11%
Digital-physical
11%
Test Data Volume
11%
Design Planning
11%
Design Migration
11%
Routing Method
10%
Power Integrity
10%
Design Requirements
10%
In-memory
10%
High Performance
9%
Flip-flop
9%
Through Silicon via
9%
Chip-package Co-design
9%
Detailed Routing
9%
Routing Behavior
8%
Deep Submicron
8%
Selective Pattern
8%
Pattern Compression
8%
Computer Science
Experimental Result
100%
Floorplanning
42%
Signal Integrity
30%
System-on-Chip
30%
Input/Output
25%
Routing Algorithm
20%
Supply Voltage
19%
Analog Circuit
19%
Integrated Circuit
17%
Field Programmable Gate Arrays
17%
Scan Chain
16%
Floorplan Design
14%
Design Package
13%
Test Data Volume
13%
Participatory Design
12%
Total Wirelength
11%
Commercial Tool
11%
Power Consumption
10%
Industrial Case
10%
Multiple Scan Chain
10%
Operational Amplifier
9%
Buffer Insertion
9%
Volume Test
8%
Power Delivery Network
8%
Global Routing
8%
Decoupling Capacitance
8%
Compression Scheme
8%
Memory Technology
8%
Performance Degradation
8%
Routing Topology
8%
through silicon vias
8%
Physical Design
8%
Linear Programming
8%
Performance Metric
8%
Machine Learning
7%
Learning System
7%
Power Supply Noise
7%
Placement Technique
7%
Routing Resource
7%
System on a Chip
7%
Agglomerative Clustering
7%
Placement Algorithm
7%
Design Constraint
7%
single-chip
7%
Routing Solution
6%
Convolutional Neural Network
6%
Energy Dissipation
6%
Routing Problem
6%
Simulated Annealing
5%
Performance Optimization
5%
Engineering
Experimental Result
81%
Package Design
24%
Interconnects
21%
Prototype
20%
Design Flow
18%
Power Supply
17%
Nanometre
17%
Nodes
16%
System-on-Chip
15%
Supply Voltage
15%
Field Programmable Gate Arrays
14%
Circuit Performance
14%
Placers
13%
Integrated Circuit
13%
Test Data
12%
Data Volume
11%
Cost Reduction
11%
Metrics
11%
Routing Algorithm
10%
Metal Layer
9%
Linear Programming
9%
Current Flow
8%
Compression Scheme
8%
Fast Turn
8%
Analog Design
8%
Analog Circuit
8%
Integrated Circuit Design
7%
Single Chip
7%
Decoupling Capacitor
7%
Design Rule
7%
Energy Dissipation
7%
Crosstalk
7%
Early Stage
7%
Ball Grid Arrays
7%
Design Complexity
7%
Design Process
7%
Optimization Technique
7%
Critical Path
6%
Simulation Result
6%
Placement Method
6%
Power Distribution
6%
Consuming Process
6%
Successive Approximation
5%
Control Scheme
5%
Test Time
5%
Search Space
5%
Routing Problem
5%
Interposer
5%
Application Specific Integrated Circuit
5%
Design Meeting
5%
