Projects per year
Personal profile
Research Interests
Electronic Design Automation, Design and Analysis of Algorithms, Combinatorial Optimization
Experience
Education/Academic qualification
PhD, University of Texas at Austin
External positions
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以記憶體為中心的人工智慧邊緣產品EDA方案: 具重新配置能力的系統評估與實作(3/3)
1/11/21 → 31/10/22
Project: Government Ministry › Ministry of Science and Technology
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Machine and Deep Learning Based Circuit and Layout Synthesis for
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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以記憶體為中心的人工智慧邊緣產品EDA方案: 具重新配置能力的系統評估與實作(2/3)
1/11/20 → 31/01/22
Project: Government Ministry › Ministry of Science and Technology
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Machine and Deep Learning Based Circuit and Layout Synthesis for
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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EDA Solutions For Memory-Centric AI Edge: System Evaluation and Implementation for Reconfigurability
1/11/19 → 31/12/20
Project: Government Ministry › Ministry of Science and Technology
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DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks
Lai, B. C., Chiang, T. C., Kuo, P. S., Wang, W. C., Hung, Y. L., Chen, H-M., Liu, C-N. & Jou, S. J., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 208-213 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An Energy-Efficient 3D Cross-Ring Accelerator with 3DSRAM Cubes for Hybrid Deep Neural Networks
Lu, W., Huang, P. T., Chen, H. M. & Hwang, W., 2021, (Accepted/In press) In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
A Style-based Analog Layout Migration Technique with Complete Routing Behavior Preservation
Chi, H. Y., Lin, Z. J., Hung, C. H., Liu, C. N. J. & Chen, H. M., Dec 2021, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review
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Improving the quality of FPGA RO-PUF by principal component analysis (PCA)
Asha, K. A., Hsu, L. E., Patyal, A. & Chen, H. M., Jul 2021, In: ACM Journal on Emerging Technologies in Computing Systems. 17, 3, 3442444.Research output: Contribution to journal › Article › peer-review
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Learning Based Placement Refinement to Reduce DRC Short Violations
Huang, Y. Y., Lin, C. T., Liang, W. L. & Chen, H. M., 19 Apr 2021, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9427321. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
1 Scopus citations