Keyphrases
Decoder
100%
Area-efficient
41%
90-nm CMOS Technology
35%
Turbo Decoder
35%
LDPC Decoder
34%
Low-density Parity-check Codes
30%
Reed-Solomon Decoder
27%
Gate Count
25%
Power Consumption
25%
Encoder-decoder Architecture
24%
Code Rate
23%
Cryptographic Processor
23%
CMOS Process
22%
Low-density Parity-check Convolutional Codes (LDPC-CCs)
21%
Reconfigurable
21%
Elliptic Curve Cryptography
21%
Reed-Solomon
20%
Codeword
19%
Energy Efficiency
19%
Viterbi Decoder
18%
LDPC Codes
18%
Low Power
18%
NAND Flash
16%
Trellis
16%
Parallel Architecture
15%
Gbps
15%
BCH Decoder
15%
Radix-4
15%
Codec
15%
LT Codes
15%
Dual-field
15%
Flash Application
15%
RS Encoder
14%
High Code Rate
14%
Interleaver
13%
Hardware Complexity
13%
Decoder Implementation
13%
Hardware Efficiency
13%
Block Size
12%
Clock Frequency
12%
Hardware Cost
12%
Non-binary LDPC Codes
12%
NAND Flash Memory
11%
Error Correction Capability
11%
Variable Node
11%
Countermeasure Circuit
10%
Berlekamp-Massey Algorithm
10%
Ripple Height
10%
IEEE 802.15.3c
10%
Differential Power Analysis
10%
Engineering
Electric Power Utilization
32%
Code Rate
29%
Parity Check Code
28%
Simulation Result
25%
Hardware Complexity
24%
Data Rate
23%
Energy Efficiency
22%
Energy Conservation
22%
Flash Memory
22%
Interleaver
19%
Decoding Algorithm
18%
Decoder Implementation
17%
Nodes
14%
Decoding Performance
14%
Convolutional Code
14%
Hardware Cost
13%
Critical Path
13%
Performance Loss
12%
Experimental Result
11%
Energy Dissipation
11%
Massey Berlekamp Algorithm
11%
Coding Gain
11%
Multiple Code
10%
Memory Access
10%
Blocklength
10%
Check Node
10%
Test Result
10%
Parity Check Matrix
9%
Product Code
9%
Cyclic Code
9%
System-on-Chip
9%
Input Symbol
9%
Forward Error-Correction
9%
Side Channel Attack
9%
Oscillator
9%
Convergence Speed
9%
Evaluator
9%
Clock Frequency
8%
Performance Degradation
8%
Supply Voltage
8%
Capacitive
8%
Parallelism
8%
Frequency Operation
8%
Readout Circuit
7%
Error Compensation
7%
Network Routing
7%
Wireless Communication
7%
Decoding Complexity
7%
Modified atmosphere packaging
7%
S2 System
7%
Computer Science
Computer Hardware
58%
Convolutional Code
25%
min-sum algorithm
24%
Energy Efficiency
23%
Power Consumption
23%
Flash Memory
22%
Parallel Architectures
21%
Power Analysis
21%
Elliptic Curve
21%
Side Channel Attack
17%
Hardware Cost
15%
High Throughput
14%
low-density parity-check code
13%
Parity Check Matrix
13%
low density parity check code
12%
Decoding Performance
11%
Experimental Result
11%
Network Routing
10%
Clock Frequency
10%
Advanced Encryption Standard
10%
Datapath
9%
Memory System
9%
Minimal Polynomial
9%
Machine Learning
9%
Energy Efficient
8%
Code Construction
8%
Forward Error Correction
8%
Ring Oscillator
8%
Decoding Throughput
7%
Decoding Algorithm
7%
Decryption
7%
Parallelism
7%
Energy Dissipation
7%
Hardware Implementation
7%
Input Symbol
7%
Message Passing
7%
Field Programmable Gate Arrays
7%
Memory Access
7%
Shifters
6%
Optical Communication
6%
Divider
6%
Very large-scale integration (VLSI) architecture
6%
radix-4
6%
Neural Network
6%
Elliptic curve scalar multiplication
6%
Critical Path
5%
Performance Loss
5%
Performance Degradation
5%
Gradient Descent
5%
Hardware Architecture
5%
