Projects per year
Personal profile
Research Interests
Mixed-signal circuit design including ADC, DAC, Audio Codec, PLL, Filters, Wireless Power, Power Management, High Speed Serial Interface, and Sensor Interfaces; Design-for-testability (DfT),built-in self-test (BIST) and calibration techniques for mixed-s
Experience
1997/6~2001/7 Project Leader Engineer, TSMC
2001/8~2004/1 Senior manager, Intellectual Property Liberty Company
2004/2~2008/8 Assistant Professor, Department of Electrical and Control Engineering, National Chiao Tung University
2008/8~2009/3 Associate Professor, Department of Electrical and Control Engineering, National Chiao Tung University
2009/3~2012/7 Associate Professor, Department of Electrical Engineering, National Chiao Tung University
2012/8~ Professor, Department of Electrical Engineering, National Chiao Tung University
Education/Academic qualification
PhD, National Tsing Hua University
External positions
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Network
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Design Of Low-power, Low-cost, And High-speed Wireline Serial Link
1/08/20 → 31/07/21
Project: Government Ministry › Ministry of Science and Technology
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Theory, verification, and applications of transfer function based analog fault model
1/08/19 → 31/07/20
Project: Government Ministry › Ministry of Science and Technology
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Theory, verification, and applications of transfer function based analog fault model
1/08/18 → 31/07/19
Project: Government Ministry › Ministry of Science and Technology
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Theory, verification, and applications of transfer function based analog fault model
1/08/17 → 31/07/18
Project: Government Ministry › Ministry of Science and Technology
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Design of very-large-scale wafer acceptance test circuits
1/08/17 → 30/11/18
Project: Government Ministry › Ministry of Science and Technology
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A 0.9 pJ/b, Reference Clock Free, Delay-Based, All-Digital Coherent BPSK Demodulator
Lo, C. Y. & Hong, H. C., 2020, In: IEEE Solid-State Circuits Letters. 3, p. 498-501 4 p., 9235385.Research output: Contribution to journal › Article › peer-review
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Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems
Hong, H-C. & Yang, C. K., Dec 2020, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 67, 12, p. 4946-4959 14 p., 9172126.Research output: Contribution to journal › Article › peer-review
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RESONANT MAGNETIC COUPLING WIRELESS POWER TRANSFER SYSTEM WITH CALIBRATION CAPABILITIES OF ITS INDUCTOR-CAPACITOR RESONANT FREQUENCIES
Hong, H-C., 14 Apr 2020, Patent No. US 10,622,841 B2Research output: Patent
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Accurate and fast on-wafer test circuitry for device array characterization in wafer acceptance test
Hong, H-C. & Lin, L. Y., 1 Sep 2019, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 9, p. 3467-3479 13 p., 8763916.Research output: Contribution to journal › Article › peer-review
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A Robust fully-integrated digital-output inductive CMOS-MEMS accelerometer with improved inductor quality factor
Chiu, Y., Liu, H. W. & Hong, H. C., 1 Nov 2019, In: Micromachines. 10, 11, 792.Research output: Contribution to journal › Article › peer-review
Open Access
Prizes
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2019 Best Master Thesis Award
Chueh, C. (Recipient) & Hong, Hao-Chiao (Recipient), 10 Feb 2020
Prize: Honorary award
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2020 Best Ph.D. dissertation award
Lin, L. Y. (Recipient) & Hong, Hao-Chiao (Recipient), 18 Jan 2021
Prize: Honorary award
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Best Paper Award, the 10th VLSI Test Technology Workshop (VTTW)
Hong, Hao-Chiao (Recipient), 13 Jul 2016
Prize
Activities
- 1 Invited talk
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Keynote speaker, 2019 Taiwan and Japan Conference on Circuits and Systems
Hao-Chiao Hong (Speaker)
20 Aug 2019Activity: Talk or presentation › Invited talk