Projects per year
Personal profile
Research Interests
Education/Academic qualification
PhD, Electronics, National Chiao Tung University
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Dive into the research topics where Chun-Jung Su is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
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Projects
- 6 Finished
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三維堆疊奈米互補式場效電晶體與記憶體元件之研製
Su, C.-J. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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三維堆疊奈米互補式場效電晶體與記憶體元件之研製
Su, C.-J. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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臺日(JP)雙邊協議型擴充加值(add-on) 國際合作研究計畫－奈米級鐵電電晶體之研究開發及其在機器學習加速器之應用
Su, C.-J. (PI)
1/04/22 → 31/03/23
Project: Government Ministry › Other Government Ministry Institute
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三維堆疊奈米互補式場效電晶體與記憶體元件之研製
Su, C.-J. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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臺日(JP)雙邊協議型擴充加值(add-on) 國際合作研究計畫－奈米級鐵電電晶體之研究開發及其在機器學習加速器之應用
Su, C.-J. (PI)
1/04/21 → 31/03/22
Project: Government Ministry › Other Government Ministry Institute
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Reviving Etch-Induced Damage on Ge MFIS via NH3 Plasma: 138% 2Pr Boost, >1000× Faster Switching, and Robust Duty-Cycle Endurance
Chen, K. Y., Lin, P. L., Su, C. J. & Su, P., 2026, 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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3D-Stackable Double-Gate Nanosheet (DGNS) FeFETs with Separate Read/Write Paths: Suppressed Variability with Sub-2 % Bit Error Rate and Mitigated Subthreshold Swing Degradation
Wu, F., Chiu, C. Y., Wu, C. H., Tsai, Y. L., Chen, S. H., Lin, H. C., Hu, V. P. H., Su, C. J. & Su, P., 2025, 2025 IEEE International Electron Devices Meeting, IEDM 2025. Institute of Electrical and Electronics Engineers Inc., (Technical Digest - International Electron Devices Meeting, IEDM).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Novel Metal-Bridging Free Lift-Off Process for Fabricating High-Performance Sub-100-nm Gate Length MoS2 Transistors
Chang, Y. C., Su, Y. C., Hu, H. C., Tsai, J. C., Shih, C. Y., Su, C. J., Li, P. W., Chang, W. H. & Lin, H. C., 2025, In: IEEE Transactions on Electron Devices. 72, 4, p. 2032-2037 6 p.Research output: Contribution to journal › Article › peer-review
1 Scopus citations -
Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors
Ma, W. C. Y., Su, C. J., Kao, K. H., Cho, T. C., Yen, Y. C., Yang, J. M., Li, Y. H., Chen, Y. C., Lin, J. Y. & Chang, H. W., 2025, In: IEEE Transactions on Electron Devices. 72, 9, p. 4865-4871 7 p.Research output: Contribution to journal › Article › peer-review
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Enabling Broader Memory Windows by Double-Gate Nanosheet Ferroelectric FETs for Next-Generation Non-Volatile Memory Storage
Wu, F., Chiu, C. Y., Lin, T. Y., Wu, C. H., Hu, V. P. H., Su, P. & Su, C. J., 2025, 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025. Institute of Electrical and Electronics Engineers Inc., (9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review