Personal profile
Education/Academic qualification
PhD, Electrical Engineering, National Taiwan University
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Dive into the research topics where Chin-Fu Nien is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
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Efficient Power- and Area-Optimized 800-Spin Ising Chip for Solving Combinatorial Optimization Problems Using Multirun Decremental Annealing
Chen, Y. H., Yen, Y. J., Nien, C. F. & Lai, C. S., 2025, In: IEEE Internet of Things Journal. 12, 20, p. 42965-42974 10 p.Research output: Contribution to journal › Article › peer-review
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Mixed-Precision Neural Network Quantization with Quantum-Inspired Annealers
Lai, C. Y., Nien, C. F., Yu, L. P. & Lai, C. S., 2025, International SoC Design Conference 2025, ISOCC 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (International SoC Design Conference 2025, ISOCC 2025 - Proceedings of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis
Liu, T. Y., Lu, Y. A., Yu, J., Nien, C. F. & Cheng, H. Y., 4 Mar 2025, ASP-DAC 2025 - 30th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 79-85 7 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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An Automated Design Platform for ReRAM-based DNN Accelerators with Hardware-Software Co-exploration
Lai, Y. C. & Nien, C. F., 2024, APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding. Institute of Electrical and Electronics Engineers Inc., p. 144-148 5 p. (APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems
Chen, Y. H., Chou, C. A., Nien, C. F. & Lin, S. Y., 2024, In: IEEE Transactions on Circuits and Systems II: Express Briefs. 71, 9, p. 4291-4295 5 p.Research output: Contribution to journal › Article › peer-review
6 Scopus citations