Projects per year
Personal profile
Research Interests
EDA, Analog Behavioral Modeling, High-level Power Modeling, Verification of System-level Integration
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Yang Ming Chiao Tung University
External positions
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- 1 Similar Profiles
Collaborations and top research areas from the last five years
Projects
- 11 Finished
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二:加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
Liu, C.-N. J. (PI)
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二:加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
Liu, C.-N. J. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二:加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
Liu, C.-N. J. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫「智慧終端裝置晶片系統與應用聯盟:數位系統的高階合成設計方法」
Liu, C.-N. J. (PI)
1/04/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems (II)
Liu, C.-N. J. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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A PVT-Resilient Subthreshold SRAM-Based In-Memory Computing Accelerator With In-Situ Regulation for Energy-Efficient Spiking Neural Networks
Kao, S. H., Hung, Y. C., Wang, I. W., Liu, B. H., Chen, Y. C., Chang, T. S., Jou, S. J., Liu, C. N., Chen, H. M. & Chen, W. Z., 2026, (Accepted/In press) In: IEEE Transactions on Circuits and Systems I: Regular Papers.Research output: Contribution to journal › Article › peer-review
Open Access -
IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs
Yang, Z., Li, S., Jin, L., Ho, T. Y. & Liu, C. N. J., 27 Mar 2026, ISPD 2026 - Proceedings of the 2026 International Symposium on Physical Design. Association for Computing Machinery, p. 11-19 9 p. (Proceedings of the International Symposium on Physical Design).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access -
An LLM-assisted Analog IC Design Tool with Automatic Topology Selection and Circuit Sizing
Nguyen, A. & Liu, C. N. J., 2025, 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2025. Institute of Electrical and Electronics Engineers Inc., (21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Efficient Guard Ring-Aware Placement for FinFET Analog Circuits with Diffusion Sharing
Chen, S. Y., Wei, T. H., Chang, H., Chen, H. M. & Liu, C. N. J., 2025, 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2025. Institute of Electrical and Electronics Engineers Inc., (21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits
Chang, S. H., Yen, R. H. & Liu, C. N., 15 Mar 2025, In: ACM Journal on Emerging Technologies in Computing Systems. 21, 2, 4.Research output: Contribution to journal › Article › peer-review
3 Scopus citations