Projects per year
Personal profile
Research Interests
EDA, Analog Behavioral Modeling, High-level Power Modeling, Verification of System-level Integration
Experience
Education/Academic qualification
PhD, National Yang Ming Chiao Tung University
External positions
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫「智慧終端裝置晶片系統與應用聯盟：數位系統的高階合成設計方法」
1/04/22 → 31/03/23
Project: Government Ministry › Ministry of Education(Include School)
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AI-Assisted Design Automation and Verification Techniques for Heterogeneous Systems (II)
1/08/21 → 31/07/22
Project: Government Ministry › Ministry of Science and Technology
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二：加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
1/08/24 → 31/07/25
Project: Government Ministry › Ministry of Science and Technology
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二：加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
1/08/23 → 31/07/24
Project: Government Ministry › Ministry of Science and Technology
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從平面到鰭式場效應電晶體的混合信號佈局合成和遷移-子計畫二：加入機器學習及佈局遷移技術的風格導向類比佈局自動化技術
1/08/22 → 31/07/23
Project: Government Ministry › Ministry of Science and Technology
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DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks
Lai, B. C., Chiang, T. C., Kuo, P. S., Wang, W. C., Hung, Y. L., Chen, H. M., Liu, C. N. & Jou, S. J., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 208-213 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
Song, L. Y., Kuo, T. C., Wang, M. H., Liu, C. N. J. & Huang, J. D., 2022, ASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 80-85 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2022-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
Fan, K. Y., Chen, J. H., Liu, C. N. & Huang, J. D., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Practical Substrate Design Considering Symmetrical and Shielding Routes
Chi, H. Y., Chen, S. Y. H., Chen, H. M., Liu, C. N., Kuo, Y. C., Chang, Y. H. & Ho, K. H., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 951-956 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Style-based Analog Layout Migration Technique with Complete Routing Behavior Preservation
Chi, H. Y., Lin, Z. J., Hung, C. H., Liu, C. N. J. & Chen, H. M., Dec 2021, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review