Projects per year
Personal profile
Research Interests
Sensor Interface Circuits, Data Converters, Phase-locked Loop and Frequency Synthesizer, High-speed Wireline Transceivers and Building Blocks, DC-DC Power Converters
Experience
2013/12~2014/11 Senior Analog Design Engineer, Mediatek USA
2015/8~2016/12 Staff Analog Design Engineer, Faraday Technology USA
2017/1~2018/8 Technical Manager, Egis Technology Inc.
2018/8~Assistant Professor, Electrical and Computer Engineering, National Chiao Tung University
Education/Academic qualification
PhD, Electrical and Computer Engineering, Oregon State University
External positions
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Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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下世代高速高解析度類比數位轉換器之功耗最佳化設計
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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下世代高速高解析度類比數位轉換器之功耗最佳化設計
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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下世代高速高解析度類比數位轉換器之功耗最佳化設計
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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High-Precision Micro-Power Analog-to-Digital Converters for IoT Sensor Interfaces
1/01/21 → 31/12/21
Project: Government Ministry › Other Government Ministry Institute
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High-Precision Micro-Power Analog-to-Digital Converters for IoT Sensor Interfaces
1/01/20 → 31/12/20
Project: Government Ministry › Other Government Ministry Institute
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A 91-dB DR 20-kHz BW 5th-Order Multi-Step Incremental ADC for Sensor Interfaces by Re-Using a MASH 2-1 Modulator
Huang, J. S., Kuo, S. C., Huang, Y. C., Kao, C. W., Hsu, C. W. & Chen, C. H., 2022, 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 2-4 3 p. (2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A 677-μW 90-dB DR 16-kHz BW Incremental ΔΣ ADC for Sensor Interfaces
Kao, C. W., Hsu, C. W., Huang, J. S., Huang, Y. C., Kuo, S. C. & Chen, C. H., 19 Apr 2021, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9427354. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A fourth-order incremental ADC in three-step
Huang, J. S., Kuo, S. C., Kao, C. W., Huang, Y. C., Hsu, C. W. & Chen, C. H., Jul 2021, In: Journal of Engineering. 2021, 7, p. 394-398 5 p.Research output: Contribution to journal › Article › peer-review
Open Access -
A Multi-Step Incremental Analog-to-Digital Converter with a Single Opamp and Two- Capacitor SAR Extended Counting
Kuo, S. C., Huang, J. S., Huang, Y. C., Kao, C. W., Hsu, C. W. & Chen, C. H., Jul 2021, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 68, 7, p. 2890-2899 10 p., 9431347.Research output: Contribution to journal › Article › peer-review
3 Scopus citations -
A Two-Step Multi-Stage Noise-Shaping Incremental Analog-to-Digital Converter (Invited Paper)
Huang, J. S., Huang, Y. C., Kao, C. W., Hsu, C. W., Chiang, S. H. W. & Chen, C. H., Aug 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 158-161 4 p. 9184542. (Midwest Symposium on Circuits and Systems; vol. 2020-August).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review