Projects per year
Personal profile
Research Interests
Applied Physical Science, Engineering Science
Education/Academic qualification
PhD, Electrical Engineering and Computer Sciences, University of California, Berkeley
External positions
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Collaborations and top research areas from the last five years
Projects
- 5 Finished
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智慧半導體奈米系統技術研究中心(5/5)
Hu, C. (PI)
1/03/22 → 31/05/23
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research (4/5)
Hu, C. (PI)
1/03/21 → 31/05/22
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research (3/5)
Hu, C. (PI)
1/03/20 → 31/05/21
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research
Hu, C. (PI)
1/03/19 → 31/05/20
Project: Government Ministry › Other Government Ministry Institute
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Intelligent Semiconductor Nanosystem Technology Research Center
Hu, C. (PI)
1/03/18 → 31/05/19
Project: Government Ministry › Other Government Ministry Institute
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A BSIM Compact Model of Two-Dimensional Semiconductor Field Effect Transistors
Chen, J. H., Pampori, A., Tung, C. T., Salahuddin, S. & Hu, C., 2025, 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025. Institute of Electrical and Electronics Engineers Inc., (9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Compact Model for Perpendicular STT-MRAM Incorporating Free and Pinned Layer Thickness Dependence, Accurate Bias Dependence, and Real-Time 3-D Switching Dynamics
Farooq Dar, M., Gagan, Sheelvardhan, K., Kumar, A., Pramanik, T., Salahuddin, S., Hu, C. & Dasgupta, A., 2025, In: IEEE Transactions on Electron Devices. 72, 8, p. 4123-4130 8 p.Research output: Contribution to journal › Article › peer-review
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A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies
Chen, J. H., Chavez, F., Tung, C. T., Khandelwal, S. & Hu, C., Jun 2025, In: Solid-State Electronics. 226, 109081.Research output: Contribution to journal › Article › peer-review
2 Scopus citations -
Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG
Chavez, F., Chen, J. H., Tung, C. T., Hu, C. & Khandelwal, S., Nov 2025, In: Solid-State Electronics. 229, 109154.Research output: Contribution to journal › Article › peer-review
Open Access -
Atomic Layer Epitaxial 2D Dielectric h-AlN as Interfacial Layer with Excellent Leakage and EOT < 1 nm for TMD-FETs
Wang, S. Y., Lin, Y. C., Huang, Y. C., Hu, C. & Chien, C. H., 2025, 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review