Projects per year
Personal profile
Research Interests
Applied Physical Science, Engineering Science
Education/Academic qualification
PhD, Electrical Engineering and Computer Sciences, University of California, Berkeley
External positions
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Dive into the research topics where Chenming Hu is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 5 Finished
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智慧半導體奈米系統技術研究中心(5/5)
Hu, C. (PI)
1/03/22 → 31/05/23
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research (4/5)
Hu, C. (PI)
1/03/21 → 31/05/22
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research (3/5)
Hu, C. (PI)
1/03/20 → 31/05/21
Project: Government Ministry › Other Government Ministry Institute
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Center for Semiconductor Technology Research
Hu, C. (PI)
1/03/19 → 31/05/20
Project: Government Ministry › Other Government Ministry Institute
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Intelligent Semiconductor Nanosystem Technology Research Center
Hu, C. (PI)
1/03/18 → 31/05/19
Project: Government Ministry › Other Government Ministry Institute
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Demonstration of Near Ideal Short Channel Effect in Lg = 25-nm Gate-All-Around Transistors Using Negative Capacitance Gate Stack
Park, J. H., Shanker, N., Hsu, S. L., Siker, U., Hu, C. & Salahuddin, S., 2026, In: IEEE Electron Device Letters. 47, 3, p. 434-437 4 p.Research output: Contribution to journal › Article › peer-review
2 Scopus citations -
Enhancement-Mode Monolayer WSe2 pFETs with Record Ion/Ioff at Contact Length of 30 nm
Su, Y. C., Wei, T. H., Lei, C., Shi, S., Hsu, Y. W., Su, T. C., Lee, S. Y., Lin, H. D., Chen, S. H., Chiang, H. L., Lin, C. C., Liu, B. H., Su, C. Y., Ke, C. C., Chang, S.-J., Wu, C. I., Hu, C., Fu, J. H., Tung, V. & Lee, T. E., 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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First Demonstration of Heterogeneous n-IGZO/p-WSe2 Integration as a Power-Performance Area Booster for BEOL Complementary Gain-Cell Memory
Lin, H. D., Su, Y. C., Su, T. C., Ambrosi, E., Wu, C. H., Kuo, C. C., Chang, C. Y., Chiang, H. L., Wei, T. H., Hsu, Y. W., Huang, C. S., Lee, S. Y., Chang, W. N., Fu, J. H., Tung, V., Sun, J. Y. C., Hu, C., Wu, C. I., Lin, C. C. & Hou, T. H. & 2 others, , 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Interfacial-Layer-Free NCFETs Achieving 2 mV Hysteresis, 27mV/dec SS, 2mV/V DIBL, and Record 2088μA/μ m Ion at VDS=Vov=0.5 V
Lin, M. K., Liang, J. Y., Liu, Y. Q., Chen, W. J., Hsu, J. Y., Wu, X. H., Dai, J. N., Chen, Y. J., Yu, B. H., Fan, Z. E., Mei, Y. M., Lee, M. H., Chu, M. W., Su, P., Hu, C. & Liu, C. W., 2026, 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Investigating contact-limited scaling in sub-15-nm TMD FETs from first-principles
Lin, K. B., Liu, H. T., Wang, S. Y., Chang, S. J., Kaun, C. C. & Hu, C., Dec 2026, In: npj Computational Materials. 12, 1, 79.Research output: Contribution to journal › Article › peer-review
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