Projects per year
Personal profile
Research Interests
High-k Dielectric for Nanoscale Devices, Organic Thin-film-transistor & Memory, Nanocrystal Nonvolatile Memory, Post-Si High-mobility Channel MOSFET
Experience
Education/Academic qualification
PhD, Electronics Engineering, National Chiao Tung University
External positions
Fingerprint
Dive into the research topics where Chao-Hsin Chien is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 1 Similar Profiles
Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
Projects
- 22 Finished
-
Research of the Vertical Stacked High Mobility Ge Channels Nanosheet Field Effect Transistor with High Quality Metal Doped into Interfacial Layer by Atomic Layer Deposition
Chien, C.-H. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
-
Research of the Vertical Stacked High Mobility Ge Channels Nanosheet Field Effect Transistor with High Quality Metal Doped into Interfacial Layer by Atomic Layer Deposition
Chien, C.-H. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
-
Process development of novel two-dimensional material: HfS2 andHfSe2 doping technology and device fabrication
Chien, C.-H. (PI)
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
-
Research of the Vertical Stacked High Mobility Ge Channels Nanosheet Field Effect Transistor with High Quality Metal Doped into Interfacial Layer by Atomic Layer Deposition
Chien, C.-H. (PI)
1/08/20 → 31/07/21
Project: Government Ministry › Other Government Ministry Institute
-
Technology Development of 4H-SiC Trench Gate MOSFET(3/3)
Chien, C.-H. (PI)
1/11/19 → 30/04/21
Project: Government Ministry › Other Government Ministry Institute
-
Achieving Sub-1 nm EOT and Enhanced Performance in Monolayer WSe2 FETs via Optimized AlN/HfO2 Dielectrics
Chih, J. H., Huang, Y. C., Pao, P. H. & Chien, C. H., 2026, In: IEEE Transactions on Electron Devices. 73, 2, p. 1063-1068 6 p.Research output: Contribution to journal › Article › peer-review
-
Contact-Length Scaling and Carrier Injection in ML MoS2 FETs with Hybrid Sb S/D Contacts
Hsu, S. H., Wu, W. C., Chien, C. H. & Li, Y., 2026, 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
-
Critical Role of In2O3 Structure and Interface in Threshold Voltage and Mobility of Oxide Semiconductor FETs
Chang, S.-J., Lee, T. E., Huang, C. S., Huang, Z. S., Arutchelvan, G., Liao, T. C., Lu, W. L., Chiu, Y. C., Shih, C. C., Lin, Q., Zhong, D., Liu, H. T., Huang, Y. C., Liao, Y. F., Hiraoka, N., Yang, C. C., Wang, C. H., Tsai, Y. W., Lin, J. M. & Haw, S. C. & 8 others, , 14 Jul 2026, In: ACS Applied Electronic Materials. 8, 13, p. 5486-5494 9 p.Research output: Contribution to journal › Article › peer-review
-
First Demonstration of Annealing-Free Atomic-Layer-Deposited In2O3 Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability
Teng, L. C., Liao, Y. C., Tian, C. C., Chen, C. C., Lin, Y. H. & Chien, C. H., 2026, In: IEEE Transactions on Electron Devices. 73, 3, p. 1381-1386 6 p.Research output: Contribution to journal › Article › peer-review
-
Improving Contact Resistance in Top-Gate Carbon Nanotube Transistor through Self-Aligned MoOxNanoparticle Contact Doping
Huang, H. Y., Chou, C. H., Chiu, H. Y., Hsu, Y. W., Wu, Q. Y., Liu, B. H., Kei, C. C. & Chien, C. H., 13 Jan 2026, In: ACS Applied Electronic Materials. 8, 1, p. 256-264 9 p.Research output: Contribution to journal › Article › peer-review
Open Access