Projects per year
Personal profile
Research Interests
SoC and VLSI System Design, Computer-aided Design, Multi-core System Design
Experience
Education/Academic qualification
PhD, Electrical Engineering, University of California, Los Angeles
External positions
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Dive into the research topics where Bo-Cheng Charles Lai is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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針對巨量深度學習模型在可重組式近記憶體運算架構上之系統編譯與架構優化技術
Lai, B.-C. C. (PI)
1/08/24 → 31/07/25
Project: Government Ministry › Other Government Ministry Institute
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針對巨量深度學習模型在可重組式近記憶體運算架構上之系統編譯與架構優化技術
Lai, B.-C. C. (PI)
1/08/23 → 31/07/24
Project: Government Ministry › Other Government Ministry Institute
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針對巨量深度學習模型在可重組式近記憶體運算架構上之系統編譯與架構優化技術
Lai, B.-C. C. (PI)
1/08/22 → 31/07/23
Project: Government Ministry › Other Government Ministry Institute
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SW/HW Acceleration Techniques For Intelligent Processing On Distributed Relational Database
Lai, B.-C. C. (PI)
1/08/21 → 31/07/22
Project: Government Ministry › Other Government Ministry Institute
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Distributed Genome Assembly Acceleration Technique for Near DRAM Computing
Lai, B.-C. C. (PI)
1/11/20 → 30/04/22
Project: Government Ministry › Other Government Ministry Institute
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Automated Optimization for FPGA-Based Sonar Object Recognition Systems
Tung, P. H., Jeng, G. S., Lai, B. C. & Hung, Y. X., 2024, APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding. Institute of Electrical and Electronics Engineers Inc., p. 349-353 5 p. (APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization
Li, B. H., Lin, K. C., Zuo, H., Pan, P. C., Chen, H. M., Jou, S. J., Liu, C. N. J. & Lai, B. C., 2024, 2024 IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024. Institute of Electrical and Electronics Engineers Inc., p. 1085-1090 6 p. (Midwest Symposium on Circuits and Systems).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform
Wu, Y. T., Yen, T. Y., Lin, Y. P. & Lai, B. C., 2024, 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 16-20 5 p. (2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Near-DRAM Accelerated Matrix Multiplications
Sinha, A. & Lai, B. C., 2024, Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024. Institute of Electrical and Electronics Engineers Inc., p. 245-248 4 p. (Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A Bin-Based Indexing for Scalable Range Join on Genomic Data
Sinha, A., Lai, B. C. & Mai, J. Y., May 2023, In: IEEE/ACM Transactions on Computational Biology and Bioinformatics. 20, 3, p. 2210-2222 13 p.Research output: Contribution to journal › Article › peer-review
2 Scopus citations