Projects per year
Personal profile
Research Interests
Semiconductor Physics & Devices, IC Technologies, Electrical Characterization Measurement & Analyses
Experience
Education/Academic qualification
PhD, National Chiao Tung University
External positions
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Dive into the research topics where Bing-Yue Tsui is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Projects
- 28 Finished
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SiC CMOS Device and IC Process Technology
1/05/20 → 30/04/21
Project: Government Ministry › Ministry of Science and Technology
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SiC CMOS Device and IC Process Technology
1/05/19 → 30/04/20
Project: Government Ministry › Ministry of Science and Technology
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SiC CMOS Device and IC Process Technology
1/05/18 → 30/04/19
Project: Government Ministry › Ministry of Science and Technology
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碳化矽單晶片功率系統平台-大型儀器(總計畫)-碳化矽蝕刻系統(碳化矽互補式金氧半場效應電晶體元件與積體電路製程技術)
1/05/18 → 30/04/19
Project: Government Ministry › Ministry of Science and Technology
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Service Proposal for Precious Instruments of National Chiao-Tung University
1/12/17 → 30/04/19
Project: Government Ministry › Ministry of Science and Technology
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High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric
Tsui, B. Y., Hung, C. L., Jhuang, Y. R., Huang, Y. T., Cheng, J. C., Lu, F. H., Shih, Y. T., Lee, Y. H., Chen, L. Y., Chuang, F. H. & Li, P. W., 19 Apr 2021, VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 9440126. (VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Degradation Mechanism of Ge N+-P Shallow Junction with Thin GeSn Surface Layer
Tsui, B. Y., Liao, H. H. & Chen, Y. J., Mar 2020, In: IEEE Transactions on Electron Devices. 67, 3, p. 1120-1125 6 p., 8964438.Research output: Contribution to journal › Article › peer-review
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Demonstration of CMOS Integration with High-Voltage Double-Implanted MOS in 4H-SiC
Jiang, J. Y., Hung, J. C., Lo, K. M., Huang, C. F., Lee, K. Y. & Tsui, B. Y., 2020, (Accepted/In press) In: Ieee Electron Device Letters.Research output: Contribution to journal › Article › peer-review
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Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics
Hung, J. H., Wang, P. Y., Lo, Y. C., Yang, C. W., Tsui, B. Y. & Yang, C. H., 2020, (Accepted/In press) In: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.Research output: Contribution to journal › Article › peer-review
Open Access -
Extraction of Ultra-Low Contact Resistivity by End-Resistance Method
Tsui, B-Y., Lee, Y. H., Wu, D. Y., Lee, Y. J. & Li, M. Y., May 2020, 2020 IEEE 33rd International Conference on Microelectronic Test Structures, ICMTS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9107910. (IEEE International Conference on Microelectronic Test Structures; vol. 2020-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review