Institute of Electronics

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  • 1994

    Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

    Ker, M.-D., Wu, C.-Y., Cheng, T., Wu, M. J. N., Yu, T. L. & Wang, A. C., 1994, p. 124-128. 5 p.

    Research output: Contribution to conference › Paper › peer-review

    9 Scopus citations
  • 1989

    Data compression for EOS on-board SAR processor

    Chang, C. Y., Fang, W.-C. & Curlander, J. C., 1 Dec 1989, p. 1723-1728. 6 p.

    Research output: Contribution to conference › Paper › peer-review

  • 1987

    CONTROLLED-AVALANCHE SUPERLATTICE TRANSISTOR.

    Chin, A. & Bhattacharya, P., 1 Dec 1987, p. 255-264. 10 p.

    Research output: Contribution to conference › Paper › peer-review

  • 1984

    MOTA - AN MOS TIMING SIMULATOR.

    Jou, S.-J., Jen, C. W., Shen, W. Z. & Lee, C. L., 1984, p. 10-11. 2 p.

    Research output: Contribution to conference › Paper › peer-review

  • PREDICTIVE VECTOR QUANTIZATION OF IMAGES.

    Hang, H.-M. & Woods, J. W., 1 Dec 1984, p. 94-98. 5 p.

    Research output: Contribution to conference › Paper › peer-review